From: Jeff McGee <jeff.mc...@intel.com>
Modify the Gen9 SSEU device status logic to support Broxton.
Broxton reuses the Skylake power gate acknowledgment registers but
has at most 1 slice and 3 subslices. Broxton supports subslice
power gating within its single slice.
Signed-off-by: Jeff McGee <jeff.mc...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 ++++++++++++++++++++++++++-----------
drivers/gpu/drm/i915/i915_reg.h | 13 ++++-------
2 files changed, 36 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c5746ef..266e4e4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4527,19 +4527,22 @@ static void gen9_sseu_device_status(struct drm_device
*dev,
struct sseu_dev_status *stat)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- const int s_max = 3, ss_max = 4;
+ int s_max = 3, ss_max = 4;
int s, ss;
u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
- s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
- s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
- s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
- eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
- eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
- eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
- eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
- eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
- eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
+ /* BXT has a single slice and at most 3 subslices. */
+ if (IS_BROXTON(dev)) {
+ s_max = 1;
+ ss_max = 3;
+ }
+
+ for (s = 0; s < s_max; s++) {
+ s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
+ eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
+ }
+
eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
GEN9_PGCTL_SSA_EU19_ACK |
GEN9_PGCTL_SSA_EU210_ACK |
@@ -4550,22 +4553,38 @@ static void gen9_sseu_device_status(struct drm_device
*dev,
GEN9_PGCTL_SSB_EU311_ACK;
for (s = 0; s < s_max; s++) {
+ unsigned int ss_cnt = 0;
+
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
stat->slice_total++;
- stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
- stat->subslice_total += stat->subslice_per_slice;
+
+ if (IS_SKYLAKE(dev))
+ ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
+
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
+ if (IS_BROXTON(dev) &&
+ !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
+ /* skip disabled subslice */
+ continue;
+
+ if (IS_BROXTON(dev))
+ ss_cnt++;
+
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
eu_mask[ss%2]);
stat->eu_total += eu_cnt;
stat->eu_per_subslice = max(stat->eu_per_subslice,
eu_cnt);
}
+
+ stat->subslice_total += ss_cnt;
+ stat->subslice_per_slice = max(stat->subslice_per_slice,
+ ss_cnt);
}
}
@@ -4600,7 +4619,7 @@ static int i915_sseu_status(struct seq_file *m, void
*unused)
memset(&stat, 0, sizeof(stat));
if (IS_CHERRYVIEW(dev)) {
cherryview_sseu_device_status(dev, &stat);
- } else if (IS_SKYLAKE(dev)) {
+ } else if (INTEL_INFO(dev)->gen >= 9) {
gen9_sseu_device_status(dev, &stat);
}
seq_printf(m, " Enabled Slice Total: %u\n",
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69d3689..34b6290 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6269,17 +6269,12 @@ enum skl_disp_power_wells {
#define CHV_POWER_SS1_SIG2 0xa72c
#define CHV_EU311_PG_ENABLE (1<<1)
-#define GEN9_SLICE0_PGCTL_ACK 0x804c
-#define GEN9_SLICE1_PGCTL_ACK 0x8050
-#define GEN9_SLICE2_PGCTL_ACK 0x8054
+#define GEN9_SLICE_PGCTL_ACK(slice) (0x804c + (slice)*0x4)
#define GEN9_PGCTL_SLICE_ACK (1 << 0)
+#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
-#define GEN9_SLICE0_SS01_EU_PGCTL_ACK 0x805c
-#define GEN9_SLICE0_SS23_EU_PGCTL_ACK 0x8060
-#define GEN9_SLICE1_SS01_EU_PGCTL_ACK 0x8064
-#define GEN9_SLICE1_SS23_EU_PGCTL_ACK 0x8068
-#define GEN9_SLICE2_SS01_EU_PGCTL_ACK 0x806c
-#define GEN9_SLICE2_SS23_EU_PGCTL_ACK 0x8070
+#define GEN9_SS01_EU_PGCTL_ACK(slice) (0x805c + (slice)*0x8)
+#define GEN9_SS23_EU_PGCTL_ACK(slice) (0x8060 + (slice)*0x8)
#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
--
2.3.3
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