Adding mailing lists (and hooray for me mixing up addresses, so now
there's a disclaimer at the bottom).
-Daniel
On 30/03/2015 21:04, Steven Honeyman wrote:
Since updating from 3.19.2 to 3.19.3 I can repeatedly cause a kernel
panic just by rebooting or powering off, but it only happens every
al
Install the test programs by default so that they can be packaged.
Tested with the testdisplay test so that it still runs after the
modifications as it depends on a data file to be present.
Packaging is useful when building a complete software stack for a
DUT from scratch. This should bring us cl
>-Original Message-
>From: Jindal, Sonika
>Sent: Tuesday, March 31, 2015 11:29 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Jindal, Sonika; R, Durgadoss; Vivi, Rodrigo
>Subject: [PATCH] drm/i915/skl: Enabling PSR2 SU with frame sync
>
>We make use of HW tracking for Selective update region
We make use of HW tracking for Selective update region and enable frame sync on
sink. We use hardware's hardcoded data values for frame sync and GTC.
v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to
i915_psr
struct, add aux_frame_sync to independently control aux frame syn
This will be utilized by next patch in this series.
Signed-off-by: Anuj Phogat
---
intel/intel_bufmgr_gem.c | 23 ++-
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 5a67f53..af44ba5 100644
--- a/intel/
Signed-off-by: Anuj Phogat
---
include/drm/i915_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index ded43b1..a6c167c 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -842,6 +842,8 @@ struct drm_i915_gem_caching {
#d
I'm still passing tiling=I915_TILING_Y in drm_intel_gem_bo_alloc_internal()
in case of YF/YS tiling. Passing tiling=I915_TILING_{YF,YS} causes bo
allocation failure. Any advice what's the right thing to do here?
Signed-off-by: Anuj Phogat
---
intel/intel_bufmgr_gem.c | 49 +++
This is required due to new macros added to i915_drm.h.
These macros are used by i965 driver.
Signed-off-by: Anuj Phogat
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 155d577..17c0e71 100644
--- a/configure.ac
+++ b/configu
Series is available at:
https://github.com/aphogat/drm.git, branch: tiling-yf-ys
Anuj Phogat (5):
i965/skl: Add macros for Yf/Ys tiling formats
i965/skl: Move tile_width computations out of
drm_intel_gem_bo_tile_pitch
i965/skl: Set tile width and height for YF/YS tiling
Align YS tile b
Signed-off-by: Anuj Phogat
---
intel/intel_bufmgr_gem.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 7c50e26..775a9f9 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -289,8 +289,13 @@ dr
From: chandra konduru
This patch is adding i-g-t test case to test panel fitting usages.
v2:
-use new tiled types when calling igt_create_fb (me)
Signed-off-by: chandra konduru
---
tests/.gitignore |1 +
tests/Android.mk |1 +
tests/Makefile.sources|1 +
test
From: chandra konduru
This patch is adding i-g-t plane scaling test case to test couple basic
display plane scaling usages. Additional test scenarios can be added later.
v2:
-Added iterative scaling to visually observe scaling (me)
v3:
-Added a flag to control primary plane scaling (me)
v4:
-U
From: chandra konduru
Adding i-g-t test case to test display crtc background color.
v2:
- Added IGT_TEST_DESCRIPTION() (Thomas Wood)
- Added to .gitignore (Thomas Wood)
- Added additional details to function header (Thomas Wood)
- Simplified igt_main (Thomas Wood)
v3:
- rebased to latest master
2015-03-26 7:19 GMT-03:00 Daniel Vetter :
> On Wed, Mar 25, 2015 at 06:50:39PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> For all those IGT tests that need an easy way to draw rectangles on
>> buffers using different methods. Current planned users: FBC and PSR
>> CRC tests.
>>
>> There
2015-03-27 13:12 GMT-03:00 Chris Wilson :
> On Fri, Mar 27, 2015 at 12:34:05PM -0300, Paulo Zanoni wrote:
>> 2015-03-27 8:01 GMT-03:00 Chris Wilson :
>> > Delay the expensive read on the FPGA_DBG register from once per mmio to
>> > once per forcewake section when we are doing the general wellbeing
On 03/27/2015 01:45 AM, Daniel Vetter wrote:
On Thu, Mar 26, 2015 at 12:41:13PM -0700, yu@intel.com wrote:
> From: Dave Gordon
>
> In order to fully initialise the default contexts, we have to execute
> batchbuffer commands on the GPU engines. But we can't do that until any
> required firm
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, March 27, 2015 5:22 PM
> To: Konduru, Chandra
> Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
> Ander
> Subject: Re: [PATCH 10/21 v2] drm/i915: Helper function to detach a scaler
> from
> a plane
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6093
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3 270/270
On Mon, Mar 30, 2015 at 04:53:38PM +0100, Thomas Wood wrote:
> diff --git a/tests/eviction_common.c b/tests/eviction_common.c
> index 4fa5c04..9e06cbb 100644
> --- a/tests/eviction_common.c
> +++ b/tests/eviction_common.c
> @@ -200,18 +200,19 @@ static void mlocked_evictions(int fd, struct
> igt_e
Add simple definitions for various macros to help spatch parse the
special igt control flow blocks and other macros correctly.
Signed-off-by: Thomas Wood
---
lib/igt-spatch.h | 41 +
lib/igt.cocci| 6 +++---
2 files changed, 44 insertions(+), 3 deleti
Signed-off-by: Thomas Wood
---
tests/core_getclient.c | 2 +-
tests/core_getstats.c | 2 +-
tests/drm_import_export.c | 2 --
tests/eviction_common.c| 7 ---
tests/gem_close_race.c | 2 +-
tests/gem_cs_prefetch.c| 2 +
On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Cleanup idr table if any error happens after __create_hw_context() in
> i915_gem_create_context()
>
> Signed-off-by: Deepak S
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
> 1 file changed,
On Mon, Mar 30, 2015 at 01:07:21PM +0300, Ville Syrjälä wrote:
> On Sat, Mar 28, 2015 at 03:23:34PM +0530, deepa...@linux.intel.com wrote:
> > From: Deepak S
> >
> > On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
> > sticky bit and it will always be set. So ignore Check for p
On Mon, Mar 30, 2015 at 03:19:29PM +0530, Ramalingam C wrote:
> Looks good to me..
>
> Reviewed-by: Ramalingam C
>
> On Friday 27 March 2015 12:51 AM, Rodrigo Vivi wrote:
> >With PSR enabled being pre computed on pipe_config we can now
> >prevent DRRS to be enabled along with PSR.
> >
> >v2: Reb
On Mon, Mar 30, 2015 at 03:45:04PM +0100, Tvrtko Ursulin wrote:
>
> On 03/30/2015 03:09 PM, Chris Wilson wrote:
> >On Mon, Mar 30, 2015 at 02:52:26PM +0100, Tvrtko Ursulin wrote:
> >>>+static void
> >>>+__i915_gem_request_retire__upto(struct drm_i915_gem_request *rq)
> >>
> >>It is a bit annoying
On Mon, Mar 30, 2015 at 01:02:50PM +0100, Chris Wilson wrote:
> On Fri, Mar 27, 2015 at 11:02:10AM +, Chris Wilson wrote:
> > Since
> >
> > commit 17cabf571e50677d980e9ab2a43c5f11213003ae
> > Author: Chris Wilson
> > Date: Wed Jan 14 11:20:57 2015 +
> >
> > drm/i915: Trim the comma
On Mon, Mar 30, 2015 at 02:35:33PM +0300, David Weinehall wrote:
> On Mon, Mar 30, 2015 at 02:05:43PM +0300, Ander Conselvan de Oliveira wrote:
> > Consistently with other free functions, handle the NULL case without
> > oopsing.
> >
> > Cc: dri-de...@lists.freedesktop.org
> > Signed-off-by: Ander
On 03/30/2015 03:09 PM, Chris Wilson wrote:
On Mon, Mar 30, 2015 at 02:52:26PM +0100, Tvrtko Ursulin wrote:
+static void
+__i915_gem_request_retire__upto(struct drm_i915_gem_request *rq)
It is a bit annoying (for readability) that it can be rq, req and request.
Nonsense they are all rq and
From: Deepak S
Cleanup idr table if any error happens after __create_hw_context() in
i915_gem_create_context()
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i9
On Monday 30 March 2015 03:37 PM, Ville Syrjälä wrote:
On Sat, Mar 28, 2015 at 03:23:34PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force off
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6092
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 270/270
On Tue, Mar 24, 2015 at 02:16:04PM +, tim.g...@intel.com wrote:
> From: Tim Gore
>
> The gem_tiled_fence_blits test tends to get oom killed
> on low memory (< 4GB) Android systems. This is because the
> test tries to allocate (sysinfo.totalram * 9 / 10) in
> buffer objects and the remaining 1
On Mon, Mar 30, 2015 at 02:52:26PM +0100, Tvrtko Ursulin wrote:
> >+static void
> >+__i915_gem_request_retire__upto(struct drm_i915_gem_request *rq)
>
> It is a bit annoying (for readability) that it can be rq, req and request.
Nonsense they are all rq and struct i915_request. Or once have been a
Am 30.03.2015 um 15:59 schrieb Ville Syrjälä:
> On Mon, Mar 30, 2015 at 03:54:29PM +0200, Thomas Richter wrote:
>> Am 30.03.2015 um 13:55 schrieb Ville Syrjälä:
>>> On Fri, Mar 27, 2015 at 07:57:52PM +0100, Thomas Richter wrote:
>>
Thanks and have a nice weekend,
>>>
>>> BTW I think this bug i
On Mon, Mar 30, 2015 at 03:54:29PM +0200, Thomas Richter wrote:
> Am 30.03.2015 um 13:55 schrieb Ville Syrjälä:
> > On Fri, Mar 27, 2015 at 07:57:52PM +0100, Thomas Richter wrote:
>
> >> Thanks and have a nice weekend,
> >
> > BTW I think this bug is about failure to restore the ivch to proper
>
Am 30.03.2015 um 13:55 schrieb Ville Syrjälä:
> On Fri, Mar 27, 2015 at 07:57:52PM +0100, Thomas Richter wrote:
>> Thanks and have a nice weekend,
>
> BTW I think this bug is about failure to restore the ivch to proper
> state after suspend (on X30):
> https://bugs.freedesktop.org/show_bug.cgi?i
Hi,
On 03/27/2015 11:01 AM, Chris Wilson wrote:
Currently, we only track the last request globally across all engines.
This prevents us from issuing concurrent read requests on e.g. the RCS
and BCS engines (or more likely the render and media engines). Without
semaphores, we incur costly stalls
+static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
+{
+ struct drm_device *dev = dev_priv->dev;
+
+ /* TODO: when DC5 support is added disable DC5 here. */
+
+ bxt_uninit_cdclk(dev);
+ bxt_enable_dc9(dev_priv);
+
+ return 0;
+}
+
static int hsw_suspen
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6091
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -4 270/270
On Fri, Mar 27, 2015 at 11:02:10AM +, Chris Wilson wrote:
> Since
>
> commit 17cabf571e50677d980e9ab2a43c5f11213003ae
> Author: Chris Wilson
> Date: Wed Jan 14 11:20:57 2015 +
>
> drm/i915: Trim the command parser allocations
>
> we may then try to allocate a zero-sized object and
This is a typical "one err bug" which is a kind of bug where there is
just one err: label which does all the error handling. One err bugs are
one of the most common class of bugs in the kernel. "Oh, we didn't
initialize that struct member" or "That pointer is NULL."
In networking they have resis
On Fri, Mar 27, 2015 at 07:57:52PM +0100, Thomas Richter wrote:
> Hi Daniel, hi Ville,
>
> thanks for your help. I used now the debug output to research how to
> enable dithering on the intel VCH. Apparently, it is bit #4 in register
> VR01 that enables dithering. This is cross-checked by enablin
The tests exercise different combinations of enabling pipe B with modes
that require more than 2 lanes and then enabling pipe C.
v2: Added a couple more tests for different pipe transitions. (Ander)
Use custom modes to make the test reliable. (Daniel)
v3: Add IGT_TEST_DESCRIPTION. (Thomas)
On Mon, Mar 30, 2015 at 02:05:43PM +0300, Ander Conselvan de Oliveira wrote:
> Consistently with other free functions, handle the NULL case without
> oopsing.
>
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/drm_atomic.c | 3 +++
> 1
On 3/26/2015 5:09 PM, R, Durgadoss wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Sonika Jindal
Sent: Thursday, March 26, 2015 1:57 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo
Subject: [Intel-gfx] [PATCH] drm/i915/sk
Consistently with other free functions, handle the NULL case without
oopsing.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/drm_atomic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm
On 30 March 2015 at 08:03, Ander Conselvan de Oliveira
wrote:
> The tests exercise different combinations of enabling pipe B with modes
> that require more than 2 lanes and then enabling pipe C.
>
> v2: Added a couple more tests for different pipe transitions. (Ander)
> Use custom modes to mak
On Mon, 2015-03-30 at 13:50 +0300, David Weinehall wrote:
> On Fri, Mar 27, 2015 at 05:36:40PM +0300, Dan Carpenter wrote:
> > Hello Ander Conselvan de Oliveira,
> >
> > This is a semi-automatic email about new static checker warnings.
> >
> > The patch 944b0c765757: "drm/i915: Copy the staged co
On 27 March 2015 at 19:18, wrote:
> From: Ville Syrjälä
>
> Add a quick test to make sure the legacy set colorkey ioctl only works
> for sprite planes.
>
> Signed-off-by: Ville Syrjälä
> ---
> lib/igt_kms.h | 4 +++
> tests/.gitignore| 1 +
> tests/Makefile.sources
On Fri, Mar 27, 2015 at 05:36:40PM +0300, Dan Carpenter wrote:
> Hello Ander Conselvan de Oliveira,
>
> This is a semi-automatic email about new static checker warnings.
>
> The patch 944b0c765757: "drm/i915: Copy the staged connector config
> to the legacy atomic state" from Mar 20, 2015, leads
Wrap the sysfs_read and sysfs_write calls in an igt_fixture block so
they are not executed during subtest enumeration.
Cc: Chris Wilson
Signed-off-by: Thomas Wood
---
tests/gem_exec_blt.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/tests/gem_exec_blt.c
Signed-off-by: Thomas Wood
---
lib/Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/Makefile.am b/lib/Makefile.am
index 4db90d4..870b1a1 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -9,7 +9,7 @@ noinst_LTLIBRARIES = libintel_tools.la
noinst_HEADERS = c
On Sat, Mar 28, 2015 at 03:23:34PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
> sticky bit and it will always be set. So ignore Check for previous
> Gfx force off during suspend and allow the force clk as part S0
Reviewed-by: Antti Koskipää
On 03/26/2015 05:35 PM, Imre Deak wrote:
> Starting from GEN5 the FBC base register is the same on all platforms.
> GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
> things work on BXT as well.
>
> Motivated by Rodrigo's request to check FBC suppo
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6090
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 270/270
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Daisy Sun
>
> Enable FBC feature on Broxton
>
> Issue: VIZ-3784
> Signed-off-by: Daisy Sun
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff -
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Daisy Sun
>
> Enable FBC feature on Broxton
>
> Issue: VIZ-3784
> Signed-off-by: Daisy Sun
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff -
Reviewed-by: Antti Koskipää
On 03/27/2015 01:07 PM, Imre Deak wrote:
> On Broxton per specification the GTT has to be mapped as uncached.
> This was caught by the PTE write readback warning, which showed a
> corrupted PTE value with using the current write-combine mapping.
>
> v2:
> - add commen
Looks good to me..
Reviewed-by: Ramalingam C
On Friday 27 March 2015 12:50 AM, Rodrigo Vivi wrote:
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
v2: Removing is_edp_psr func that is not used after this patch.
Rename match_conditions and
On Sat, Mar 28, 2015 at 03:23:38PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Based on the spec, Setting up static BIAS for GPU to improve the
> rps performace.
My understanding is that this would only improve the GPU performance
under TDP constrained use cases, at the cost of C
Looks good to me..
Reviewed-by: Ramalingam C
On Friday 27 March 2015 12:51 AM, Rodrigo Vivi wrote:
With PSR enabled being pre computed on pipe_config we can now
prevent DRRS to be enabled along with PSR.
v2: Rebase after changing previous patch
Cc: Ramalingam C
Signed-off-by: Rodrigo Vivi
On Sat, Mar 28, 2015 at 11:07:09AM +0100, Thomas Richter wrote:
> Hi folks,
>
> this is a patch against drm-intel-nightly that enables an apparently
> undocumented feature of the intel VCH DVO chips. Bit 4 of the VR01
> register controls an automatic dithering for 18bpp outputs which greatly
>
On Fri, Mar 27, 2015 at 07:59:40PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The legcy colorkey ioctls are only implemented for sprite planes, so
> reject the ioctl for primary/cursor planes. If we want to support
> colorkeying with these planes (assuming we have hw su
On Fri, Mar 27, 2015 at 06:51:57PM +, Vivi, Rodrigo wrote:
> Thanks
>
> Reviewed-by: Rodrigo Vivi
> Tested-by: Rodrigo Vivi
Queued for -next, thanks for the patch.
-Daniel
>
> On Fri, 2015-03-27 at 17:21 +0530, Durgadoss R wrote:
> > BSpec recommends to keep the main link state consistent
On Mon, Mar 30, 2015 at 10:18:53AM +0200, Thomas Richter wrote:
> Hi Daniel, hi Ville,
>
> did you get the attached patch? This enables dithering for the iVCH DVO
> chip and improves image quality for 24 pipes on 18bpp displays greatly.
>
> Thanks for reviewing and considering this patch.
Yeah t
On Mon, Mar 30, 2015 at 10:41:19AM +0300, Ander Conselvan de Oliveira wrote:
> Users of the atomic state assume that if the pointer to a crtc, plane or
> connector is not NULL in the respective object vector, than the state
> for that object in *_states vector also won't be NULL. That assumption
>
On Sat, Mar 28, 2015 at 11:07:09AM +0100, Thomas Richter wrote:
> Hi folks,
>
> this is a patch against drm-intel-nightly that enables an apparently
> undocumented feature of the intel VCH DVO chips. Bit 4 of the VR01 register
> controls an automatic dithering for 18bpp outputs which greatly impro
Adding 90/270 rotation testcase for primary and sprite planes.
v2: Added position test for sprite. Checking for gen > 9 for 90/270.
Some cleanup and rebase.
Signed-off-by: Sonika Jindal
---
tests/kms_rotation_crc.c | 175 +-
1 file changed, 142 inser
v2: Moving creation of property in a function, checking for 90/270
rotation simultaneously (Chris)
Letting primary plane to be positioned
v3: Adding if/else for 90/270 and rest params programming, adding check for
pixel_format, some cleanup (review comments)
v4: Adding right pixel_formats, using sr
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_display.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ceb2e61..f0bbc22 100644
--- a/drivers/gpu/drm/i915/intel_display.c
Hi Daniel, hi Ville,
did you get the attached patch? This enables dithering for the iVCH DVO
chip and improves image quality for 24 pipes on 18bpp displays greatly.
Thanks for reviewing and considering this patch.
Thomas Richter
>From 3d0b1a15302aa704c7cf4ebbf7c2b8a1566b9beb Mon Sep 17 00:00:00
On Mon, Mar 30, 2015 at 08:54:55AM +0200, Daniel Vetter wrote:
> On Fri, Mar 27, 2015 at 08:18:28AM -0700, Jesse Barnes wrote:
> > On 03/27/2015 01:04 AM, Daniel Vetter wrote:
> > > On Fri, Mar 27, 2015 at 08:39:56AM +0200, Jani Nikula wrote:
> > >> On Thu, 26 Mar 2015, Tommi Rantala wrote:
> > >>
On Fri, 2015-03-27 at 17:36 +0300, Dan Carpenter wrote:
> Hello Ander Conselvan de Oliveira,
>
> This is a semi-automatic email about new static checker warnings.
>
> The patch 944b0c765757: "drm/i915: Copy the staged connector config
> to the legacy atomic state" from Mar 20, 2015, leads to the
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6087
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 270/270
Users of the atomic state assume that if the pointer to a crtc, plane or
connector is not NULL in the respective object vector, than the state
for that object in *_states vector also won't be NULL. That assumption
was broken by drm_atomic_state_clear(), which would clear the state
pointer but leave
On Mon, Mar 30, 2015 at 08:33:12AM +0300, Ander Conselvan de Oliveira wrote:
> Makes that code atomic ready.
>
> v2: Acquire crtc_state for the "other" pipe only when needed. (Daniel)
>
> v3: Really only acquire the other state if necessary. (Daniel)
Missing sob added and queued for -next, thank
So that it is possible to use a custom mode with the simplified mode set API.
v2: Add documentation for igt_output_override_mode(). (Thomas)
---
lib/igt_kms.c | 18 ++
lib/igt_kms.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 6cb1f
The tests exercise different combinations of enabling pipe B with modes
that require more than 2 lanes and then enabling pipe C.
v2: Added a couple more tests for different pipe transitions. (Ander)
Use custom modes to make the test reliable. (Daniel)
v3: Add IGT_TEST_DESCRIPTION. (Thomas)
78 matches
Mail list logo
