Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
intel/intel_bufmgr_gem.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 7c50e26..775a9f9 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -289,8 +289,13 @@ drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem
*bufmgr_gem, unsigned long size,
if (*tiling_mode == I915_TILING_NONE)
return size;
+ /* Tiled surface base addresses must be tile aligned (64KB aligned
+ * for TileYS, 4KB aligned for all other tile modes).
+ */
+ if (*tiling_mode == I915_TILING_YS)
+ return ROUND_UP_TO(size, 64 * 1024);
/* 965+ just need multiples of page size for tiling */
- if (bufmgr_gem->gen >= 4)
+ else if (bufmgr_gem->gen >= 4)
return ROUND_UP_TO(size, 4096);
/* Older chips need powers of two, of at least 512k or 1M */
--
2.3.4
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