On Thu, 26 Mar 2015, Tommi Rantala wrote:
> Fix definition of the DRM_IOCTL_I915_GET_SPRITE_COLORKEY ioctl, so that it
> is different from the DRM_IOCTL_I915_SET_SPRITE_COLORKEY ioctl.
>
> Signed-off-by: Tommi Rantala
Whoa. Broken since its introduction in
commit 8ea30864229e54b01ac0e9fe88c4b73
Hi,
On to, 2015-03-26 at 16:14 +, Chris Wilson wrote:
> On Thu, Mar 26, 2015 at 06:05:27PM +0200, Joonas Lahtinen wrote:
> > Install the test programs by default so that they can be packaged.
> >
> > v2:
> > - Install more tests including scripts and their data
>
> Packaged by whom?
>
> Dev
On 3/27/2015 12:50 AM, Rodrigo Vivi wrote:
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
v2: Removing is_edp_psr func that is not used after this patch.
Rename match_conditions and document it since it is now external.
Moving to a pr
On Friday 27 March 2015 02:32 AM, Paulo Zanoni wrote:
2015-03-19 11:14 GMT-03:00 :
From: Deepak S
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
I was told that my review comments were sent to the p
On Friday 27 March 2015 03:13 AM, Chris Wilson wrote:
On Thu, Mar 26, 2015 at 06:32:15PM -0300, Paulo Zanoni wrote:
2015-03-19 11:14 GMT-03:00 :
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe &
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6066
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 276/276
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6060
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 270/270
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6065
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 276/276
On Thu, Mar 26, 2015 at 05:40:07PM -0400, Josh Boyer wrote:
> On Mon, Mar 2, 2015 at 4:30 AM, Jani Nikula wrote:
> >
> > Stable team, please backport
> >
> > commit f9b61ff6bce9a44555324b29e593fdffc9a115bc
> > Author: Daniel Vetter
> > Date: Wed Jan 7 13:54:39 2015 +0100
> >
> > drm/i915: P
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6063
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 276/276
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6063
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 276/276
On Fri, 27 Mar 2015, Jani Nikula wrote:
> From: "A.Sunil Kamath"
>
> For BXT gmbus is pulled from GPU to CPU. From implementation point of
> view only pin pair configuration will change. The existing
> implementation supports all platforms previous to GEN8 and also SKL. But
> for BXT pin pair con
On Thu, 26 Mar 2015, Jani Nikula wrote:
> On Tue, 17 Mar 2015, Imre Deak wrote:
>> From: "A.Sunil Kamath"
>>
>> Though we populate all gmbus ports during setup_gmbus, only
>> valid ones should be registered to i2c adapters. This is
>> important as userspace can directly interact with the i2c bus
This will be helpful for adding future platforms. It is better to keep
the information in the single point of truth (the table) instead of
duplicating it into the validity function.
While at it, add dev_priv parameter to the function, also to prepare for
adding future platform support.
Signed-off
From: "A.Sunil Kamath"
For BXT gmbus is pulled from GPU to CPU. From implementation point of
view only pin pair configuration will change. The existing
implementation supports all platforms previous to GEN8 and also SKL. But
for BXT pin pair configuration is completely different than SKL or other
Index the gmbus tables directly using the pin instead of having a
confusing "port = i + 1" mapping. This finishes off removing the "gmbus
port" as a notion, and leaves us with just the "gmbus pin".
As pin 0 is invalid by definition and the gmbus tables will have a gap
at that index, add pin validi
Hi all, Imre in particular -
This series spun out of reviewing the bxt gmbus enabling patches [1],
[2] and [3] that were getting, at least for my poor brain, hard to
follow.
The first four are platform independent cleanup and prep work that could
be merged before any of the bxt enabling series. I
The specs refer to pin pairs. Start moving towards using pin rather than
port all around to avoid confusion. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 20 ++--
drivers/gpu/drm/i915/intel_bi
Rename intel_gmbus_is_port_valid to intel_gmbus_is_valid_pin, and rename
port parameters to pin as well. This matches usage all around, as
usually a pin is passed to the validity check function. No functional
changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 8
Legacy setCrtc has a nice fastpath for just updating the frontbuffer
when the output routing doesn't change. Which I of course tried to
keep working, except that I fumbled the job: The helpers correctly
compute ->mode_changed, CRTC updates get correctly skipped but
connector functions are called un
On Thu, Mar 26, 2015 at 06:32:15PM -0300, Paulo Zanoni wrote:
> 2015-03-19 11:14 GMT-03:00 :
> > From: Deepak S
> >
> > After feedback from the hardware team, now we set the GPU min/idel freq to
> > RPe.
> > Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
> > frequency to
On Mon, Mar 2, 2015 at 4:30 AM, Jani Nikula wrote:
>
> Stable team, please backport
>
> commit f9b61ff6bce9a44555324b29e593fdffc9a115bc
> Author: Daniel Vetter
> Date: Wed Jan 7 13:54:39 2015 +0100
>
> drm/i915: Push vblank enable/disable past encoder->enable/disable
>
> to 3.19.
>
> Bugzil
2015-03-19 11:14 GMT-03:00 :
> From: Deepak S
>
> After feedback from the hardware team, now we set the GPU min/idel freq to
> RPe.
> Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
> frequency to RPn, punit is failing to change the input voltage to
> minimum :(
Since thi
On Thu, Mar 26, 2015 at 05:43:33PM +, Tvrtko Ursulin wrote:
> >-static int
> >-i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
> >-{
> >-if (!obj->active)
> >-return 0;
> >-
> >-/* Manually manage the write flush as we may have not yet
> >- * retire
On Thu, Mar 26, 2015 at 12:22:07PM -0700, Rodrigo Vivi wrote:
> Let userspace know the status of Panel Self-Refresh by virtue of a
> property on the appropriate connector.
>
> v2: Only attach the property if the driver is capable of PSR.
> v3: Add docbook courtesy of Damien.
> v4: Mark the initial
2015-03-19 11:14 GMT-03:00 :
> From: Deepak S
>
> After feedback from the hardware team we are changing the RC6
> promotional timer to increase the power saving without
> changing performance.
I was told that my review comments were sent to the previous
submission of this patch. So just to docum
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6061
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 276/276
Hello,
Trinity discovered oopses with the i915 colorkey ioctls, reproducible
on my system with this:
#include
#include
#include
#include
#include
#include
#include
#include
#define GET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY,
struct drm_intel_sprite_colorkey)
int main(i
Fix definition of the DRM_IOCTL_I915_GET_SPRITE_COLORKEY ioctl, so that it
is different from the DRM_IOCTL_I915_SET_SPRITE_COLORKEY ioctl.
Signed-off-by: Tommi Rantala
---
include/uapi/drm/i915_drm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/drm/i915_drm.h
From: Alex Dai
Now print out Bootrom, uKernel and MIA Core status. The scratch reg
0 & 15 are used for communication between driver and firmware. Their
status is also printed out.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_debugfs.c | 73 +
From: Alex Dai
Set the firmware version that required by HW. Driver sets required
version according to platform. After firmware is loaded but before
send to HW, the major.minor version is read from CSS header field,
which is 17th DWORD currently. The major version must be same; the
minor version
From: Alex Dai
To enable GuC command submission / scheduling, we need to setup
firmware initializaion properly. i915.enable_guc_scheduling is
introduced to enable / disable GuC submission.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/g
From: Alex Dai
All gem objects used by GuC are pinned to ggtt space out of range
[0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is
used internally for its Boot ROM, SRAM etc. Currently this WPOCM
size is 512K. This is done by using of PIN_OFFSET_BIAS.
Issue: VIZ-4884
Signed-off-b
From: "Michael H. Nguyen"
Move defines from intel_lrc.c to i915_reg.h so they are
accessible by the guc files
Issue: VIZ-4884
Signed-off-by: Michael H. Nguyen
---
drivers/gpu/drm/i915/i915_reg.h | 68
drivers/gpu/drm/i915/intel_lrc.c | 67 -
From: Alex Dai
Add functions to submit work queue item and ring the door bell.
GuC TLB needs to be invalided if LRC context changes.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc.h | 3 +
drivers/gpu/drm/i915/intel_guc_client.c| 175
From: Alex Dai
GuC firmware uses the one page after Ring Context as shared data.
However, GuC uses same offset to address this page for all rings.
So we have to allocate same size of lrc context for all rings.
Also, reduce ring buffer size to 4 pages. In GuC, work queue tail is
referenced by 11
From: Alex Dai
Whenever RC6 state (0xA210) is changed, driver needs to notify GuC
via guc_action.
Issue: VIZ-4884
Change-Id: I15c661a915c670691d020471ecaccb00f7afb624
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_guc_api.h | 1
From: Sagar Kamble
Need to take forcewake before GuC loading.
Issue: VIZ-4884
Change-Id: Ie422fc1e122933b161ff63cab23622197e6bba54
Signed-off-by: Sagar Kamble
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loade
From: Dave Gordon
Factor out the common code of loading firmware into a new file,
leaving only the uC-specific parts in the GuC loaders.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/intel_uc_loader.
From: Alex Dai
This series of patch is to enable ExecList submission via GuC. Here are some
key points related to this series, not in particular order.
*** i915_guc_client ***
We use the term client to avoid confusion with contexts. A i915_guc_client is
equivalent to GuC object guc_context_desc.
From: Alex Dai
These are the subset of GuC interface that we are going to use to
enable command submission through GuC. The definition of these
struct and bit setting need to match those in firmware.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc_api.h | 217 +++
From: Alex Dai
Allocate a gem obj to hold GuC log data. Also a debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_debugfs.c| 29 +++
drivers/gpu/drm/i915/i915_drv.h
From: Dave Gordon
In order to fully initialise the default contexts, we have to execute
batchbuffer commands on the GPU engines. But we can't do that until any
required firmware has been loaded, which may not be possible during
driver load, because the filesystem(s) containing the firmware may no
From: Alex Dai
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_reg.h| 11 --
drivers/gpu/drm/i915/intel_guc.h | 7
drivers/gpu/drm/i915/intel_guc_s
From: Alex Dai
Implementation of GuC client. A GuC client has its own doorbell
and workqueue. It maintains the doorbell cache line, process
description object and work queue item.
A default guc_client is created to do the in-order legacy execlist
submission.
Issue: VIZ-4884
Signed-off-by: Alex
From: Alex Dai
These functions will be used by GuC scheduler.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_lrc.c | 6 +++---
drivers/gpu/drm/i915/intel_lrc.h | 3 +++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/dri
From: Alex Dai
Add GuC firmware loader. It uses the unified firmware loader to
fetch firmware blob first, then load to hw in driver main thread.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_dma.c | 6 +
driver
From: "Michael H. Nguyen"
i915_gem_object_write() is a generic function to copy data from
user memory to gem object.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_gem.c | 30 ++
2 files changed, 33 in
Let userspace know the status of Panel Self-Refresh by virtue of a
property on the appropriate connector.
v2: Only attach the property if the driver is capable of PSR.
v3: Add docbook courtesy of Damien.
v4: Mark the initial value as 'unsupported' - it will be determined
correctly when we late
With PSR enabled being pre computed on pipe_config we can now
prevent DRRS to be enabled along with PSR.
v2: Rebase after changing previous patch
Cc: Ramalingam C
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
d
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
v2: Removing is_edp_psr func that is not used after this patch.
Rename match_conditions and document it since it is now external.
Moving to a propper place as pointed out by Sivakumar.
Use
Hi,
On 03/19/2015 08:59 AM, Chris Wilson wrote:
Currently, we only track the last request globally across all engines.
This prevents us from issuing concurrent read requests on e.g. the RCS
and BCS engines (or more likely the render and media engines). Without
semaphores, we incur costly stalls
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6058
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 276/276
On 26 March 2015 at 16:05, Joonas Lahtinen
wrote:
> Install the test programs by default so that they can be packaged.
Could you also explain why the tests should be packaged?
>
> v2:
> - Install more tests including scripts and their data
>
> Signed-off-by: Joonas Lahtinen
> ---
> tests/Make
On 03/26/2015 06:22 AM, Daniel Vetter wrote:
> On Mon, Mar 23, 2015 at 12:13:56PM +, John Harrison wrote:
>> On 23/03/2015 09:22, Daniel Vetter wrote:
>>> On Fri, Mar 20, 2015 at 09:11:35PM +, Chris Wilson wrote:
On Fri, Mar 20, 2015 at 05:48:36PM +, john.c.harri...@intel.com wrote
On Tue, 17 Mar 2015, Imre Deak wrote:
> From: "A.Sunil Kamath"
>
> Though we populate all gmbus ports during setup_gmbus, only
> valid ones should be registered to i2c adapters. This is
> important as userspace can directly interact with the i2c bus.
>
> While populating gmbus register we ensure
On Fri, Mar 20, 2015 at 04:18:13PM +0200, Ander Conselvan de Oliveira wrote:
> Move towards atomic by using the legacy modeset's drm_atomic_state
> instead.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 17 +++--
> 1 file changed, 11
On Fri, Mar 20, 2015 at 04:18:12PM +0200, Ander Conselvan de Oliveira wrote:
> Instead of using connector->new_encoder, get the same information from
> the pipe_config, thus making the function ready for the atomic
> conversion.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/g
On Thu, Mar 26, 2015 at 05:46:22PM +0100, Daniel Vetter wrote:
> On Fri, Mar 20, 2015 at 04:18:09PM +0200, Ander Conselvan de Oliveira wrote:
> > Move towards atomic by using the legacy modeset's drm_atomic_state
> > instead.
> >
> > Signed-off-by: Ander Conselvan de Oliveira
> >
> > ---
> > dr
On Fri, Mar 20, 2015 at 04:18:09PM +0200, Ander Conselvan de Oliveira wrote:
> Move towards atomic by using the legacy modeset's drm_atomic_state
> instead.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_display.c | 12
> 1 file changed, 8 inser
On Fri, Mar 20, 2015 at 04:18:08PM +0200, Ander Conselvan de Oliveira wrote:
> Move towards atomic by using the legacy modeset's drm_atomic_state
> instead.
>
> v2: Move call to drm_atomic_add_affected_connectors() to
> intel_modeset_compute_config(). (Daniel)
>
> Signed-off-by: Ander Conselv
On Thu, Mar 26, 2015 at 06:05:27PM +0200, Joonas Lahtinen wrote:
> Install the test programs by default so that they can be packaged.
>
> v2:
> - Install more tests including scripts and their data
Packaged by whom?
Developers should be using git (otherwise how will they feed back the
patches th
On Thu, Mar 26, 2015 at 04:09:09PM +, Lionel Landwerlin wrote:
>
> Chris,
>
> Here is another iteration/rebase on top of nightly of your read-read
> optimisations patch.
>
> The main change is replacing the refcount for the active field of the
> drm_i915_gem_object with a bit field (1 bit pe
Chris,
Here is another iteration/rebase on top of nightly of your read-read
optimisations patch.
The main change is replacing the refcount for the active field of the
drm_i915_gem_object with a bit field (1 bit per engine).
This was tested with ChromiumOS by using a bunch of webgl demos
running
From: Chris Wilson
Currently, we only track the last request globally across all engines.
This prevents us from issuing concurrent read requests on e.g. the RCS
and BCS engines (or more likely the render and media engines). Without
semaphores, we incur costly stalls as we synchronise between ring
Install the test programs by default so that they can be packaged.
v2:
- Install more tests including scripts and their data
Signed-off-by: Joonas Lahtinen
---
tests/Makefile.am | 22 +++---
tests/Makefile.sources | 10 --
2 files changed, 27 insertions(+), 5 deleti
Michel Thierry writes:
> The first 2 patches are fixes from the previous patchset, reported by static
> analysis tools, while the last 2 patches complete the required work for
> gen6/7.
>
> I've also started changing the authorship of the patches as suggested by
> Daniel.
>
> Michel Thierry (5)
Starting from GEN5 the FBC base register is the same on all platforms.
GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
things work on BXT as well.
Motivated by Rodrigo's request to check FBC support on BXT.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_gem_stolen.c
On Fri, Mar 20, 2015 at 04:18:05PM +0200, Ander Conselvan de Oliveira wrote:
> @@ -10136,6 +10157,8 @@ static void intel_modeset_commit_output_state(struct
> drm_device *dev)
> crtc->base.state->enable = crtc->new_enabled;
> crtc->base.enabled = crtc->new_enabled;
>
On Thu, Mar 26, 2015 at 10:30:21PM +0800, kbuild test robot wrote:
> drivers/gpu/drm/i915/intel_pm.c:2913:4-5: Unneeded semicolon
>
>
> Removes unneeded semicolon.
>
> Generated by: scripts/coccinelle/misc/semicolon.cocci
>
> CC: Tvrtko Ursulin
> Signed-off-by: Fengguang Wu
Oops, somehow di
Introduce in
commit 1fc0a8f7c45275c38d3322089313fe2e309c1f17
Author: Tvrtko Ursulin
Date: Mon Mar 23 11:10:38 2015 +
drm/i915/skl: Take 90/270 rotation into account in watermark calculations
spotted by the 0-day builder.
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: kbuild test robot
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6057
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 276/276
On Wednesday 25 March 2015 12:42 AM, Rodrigo Vivi wrote:
Let's pre-compute it on pipe_config compute to let it exported there but also
to use to see if we can enable DRRS.
Cc: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 35
On Wednesday 25 March 2015 09:11 PM, Vivi, Rodrigo wrote:
On Wed, 2015-03-25 at 16:08 +0530, Ramalingam C wrote:
On Wednesday 25 March 2015 12:42 AM, Rodrigo Vivi wrote:
With PSR enabled being pre computed on pipe_config we can now
prevent DRRS to be enabled along with PSR.
Cc: Ramalingam C
drivers/gpu/drm/i915/intel_pm.c:2913:4-5: Unneeded semicolon
Removes unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
CC: Tvrtko Ursulin
Signed-off-by: Fengguang Wu
---
intel_pm.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/gpu/drm/i915/
On Wed, Mar 25, 2015 at 07:27:16PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Replace the hardcoded 9 with a call to intel_freq_opcode(450).
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 1 file cha
On Wed, Mar 25, 2015 at 08:37:29PM +, Vivi, Rodrigo wrote:
> Also talking about visible names I'm not sure about "Idle" as well...
> Every time I read it get confused... I believe it is because PSR active
> needs Idle usage...
>
> What do you think about changing to Idle to Enable-Exit and Act
On 03/26/2015 01:30 PM, Ville Syrjälä wrote:
On Thu, Mar 26, 2015 at 12:39:40PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
intel_user_framebuffer_destroy() requires the struct_mutex for its
object bookkeeping, so this means that all calls to
drm_framebuffer_unreference must be held wit
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Thursday, March 26, 2015 9:13 PM
> To: He, Shuang
> Cc: Daniel Vetter; Gao, Ethan; intel-gfx@lists.freedesktop.org;
> daniel.vet...@ffwll.ch
> Subject: Re: [Intel-gfx] [PATCH] drm
On Thu, Mar 26, 2015 at 12:39:40PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> intel_user_framebuffer_destroy() requires the struct_mutex for its
> object bookkeeping, so this means that all calls to
> drm_framebuffer_unreference must be held without that lock.
>
> This is a simplifi
On Thu, Mar 26, 2015 at 02:14:39PM +0100, Daniel Vetter wrote:
> On Thu, Mar 26, 2015 at 01:20:50PM +0200, Ville Syrjälä wrote:
> > On Thu, Mar 26, 2015 at 11:03:55AM +0100, Daniel Vetter wrote:
> > > On Thu, Mar 26, 2015 at 09:35:10AM +0200, Ville Syrjälä wrote:
> > > > On Wed, Mar 25, 2015 at 06:
On Mon, Mar 23, 2015 at 12:13:56PM +, John Harrison wrote:
> On 23/03/2015 09:22, Daniel Vetter wrote:
> >On Fri, Mar 20, 2015 at 09:11:35PM +, Chris Wilson wrote:
> >>On Fri, Mar 20, 2015 at 05:48:36PM +, john.c.harri...@intel.com wrote:
> >>>From: John Harrison
> >>>
> >>>The intende
On Thu, Mar 26, 2015 at 01:20:50PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 26, 2015 at 11:03:55AM +0100, Daniel Vetter wrote:
> > On Thu, Mar 26, 2015 at 09:35:10AM +0200, Ville Syrjälä wrote:
> > > On Wed, Mar 25, 2015 at 06:47:21PM -0300, Paulo Zanoni wrote:
> > > > 2015-03-25 17:15 GMT-03:00 D
On Thu, Mar 26, 2015 at 11:08:00AM +, He, Shuang wrote:
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > Vetter
> > Sent: Thursday, March 26, 2015 6:24 PM
> > To: He, Shuang
> > Cc: Gao, Ethan; intel-gfx@lists.freedesktop.org; daniel
From: Tvrtko Ursulin
intel_user_framebuffer_destroy() requires the struct_mutex for its
object bookkeeping, so this means that all calls to
drm_framebuffer_unreference must be held without that lock.
This is a simplified version of the identically named patch by Chris Wilson.
References: https:
On Thu, Mar 26, 2015 at 12:47:15PM +0100, Daniel Vetter wrote:
> In spirit with
>
> commit 5724dbd1678e2f573b13f0688277941fad66cb88
> Author: Damien Lespiau
> Date: Tue Jan 20 12:51:52 2015 +
>
> drm/i915: Rename plane_config to initial_plane_config
>
> to make it clear that this code
On Thu, Mar 26, 2015 at 11:31:35AM +, Tvrtko Ursulin wrote:
>
> On 03/25/2015 01:45 PM, Daniel Vetter wrote:
> >On Tue, Mar 24, 2015 at 08:50:34PM +, Chris Wilson wrote:
> >>On Tue, Mar 24, 2015 at 12:40:09PM -0700, Rodrigo Vivi wrote:
> >>>This flag was being mostly used as a meta flag in
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6054
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 276/276
On Wed, 25 Mar 2015, Daniel Vetter wrote:
> This is a very similar bug in the load detect code fixed in
>
> commit 9128b040eb774e04bc23777b005ace2b66ab2a85
> Author: Daniel Vetter
> Date: Tue Mar 3 17:31:21 2015 +0100
>
> drm/i915: Fix modeset state confusion in the load detect code
>
> But
On Wed, 25 Mar 2015, Josh Boyer wrote:
> On Wed, Mar 25, 2015 at 1:17 PM, Daniel Vetter wrote:
>> On Wed, Mar 25, 2015 at 12:42:46PM -0400, Josh Boyer wrote:
>>> > I'll try that a bit later today. Out of sheer curiosity, I folded
>>> > commit5ba76c41e55c (drm/i915: Put update_state_fb() next to
On Wed, 25 Mar 2015, Daniel Vetter wrote:
> On Tue, Mar 24, 2015 at 12:10:28PM -0400, Josh Boyer wrote:
>> OK, with that commit applied I no longer get the kref.h splat and the
>> NUC machine boots headless. I still see the backtrace below on both
>> the NUC and the macbook. I have a copy of it
Hi Dave -
This should cover the final warnings in -rc5 with two more backports
from our development branch (drm-intel-next-queued). They're the ones
from Daniel and Damien, with references to the reports.
This is on top of drm-fixes because of the dependency on the two earlier
fixes not yet in L
In spirit with
commit 5724dbd1678e2f573b13f0688277941fad66cb88
Author: Damien Lespiau
Date: Tue Jan 20 12:51:52 2015 +
drm/i915: Rename plane_config to initial_plane_config
to make it clear that this code is all special-purpose for the initial
plane takeover.
Cc: Damien Lespiau
Cc:
Currently we only set preserve_bios_swizzling when the initial fb is
shared and totally miss the single-screen case. Fix this by
consolidating all the logic for both cases.
This seems to go back to when swizzle preservation was originally
merged in
commit d9ceb8163339134bd3ffb9fb87a0db4698283e32
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Sonika Jindal
>Sent: Thursday, March 26, 2015 1:57 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH] drm/i915/skl: Enabling PSR2 SU with frame sync
>
>
On 03/25/2015 01:45 PM, Daniel Vetter wrote:
On Tue, Mar 24, 2015 at 08:50:34PM +, Chris Wilson wrote:
On Tue, Mar 24, 2015 at 12:40:09PM -0700, Rodrigo Vivi wrote:
This flag was being mostly used as a meta flag in some
cases and not covering other cases.
One of the risks is that it was m
On Thu, Mar 26, 2015 at 11:03:55AM +0100, Daniel Vetter wrote:
> On Thu, Mar 26, 2015 at 09:35:10AM +0200, Ville Syrjälä wrote:
> > On Wed, Mar 25, 2015 at 06:47:21PM -0300, Paulo Zanoni wrote:
> > > 2015-03-25 17:15 GMT-03:00 Daniel Vetter :
> > > > And use the same colors for both flip and fills
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Thursday, March 26, 2015 6:24 PM
> To: He, Shuang
> Cc: Gao, Ethan; intel-gfx@lists.freedesktop.org; daniel.vet...@ffwll.ch
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fixup lega
On Tue, Jan 27, 2015 at 09:38:23PM +, Chris Wilson wrote:
> On Tue, Jan 27, 2015 at 04:33:01PM +, Patrick Welche wrote:
> > On shutdown, my sandy bridge laptop hangs in an infinite loop in:
> > xf86-video-intel/src/sna/sna_threads.c:
> >
> > 69 while (t->func == NULL)
On Thu, Mar 26, 2015 at 02:53:10AM -0700, shuang...@intel.com wrote:
> Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
> shuang...@intel.com)
> Task id: 6053
> -Summary-
> Platform Delta drm-int
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