From: Ville Syrjälä
DDR DVFS introduces massive memory latencies which can't be handled by the PND
deadline stuff. Instead the watermarks will need to be programmed to compensate
for the latency and the deadlines will need to be programmed to tight fixed
values. That means DDR DVFS can only
-
Message: 2
Date: Thu, 26 Feb 2015 21:01:04 +0200
From: ville.syrj...@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 12/12] drm/i915: Enable the maxfifo PM5
modewhen appropriate on CHV
Message-ID:
<1424977264-2
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5863
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -7 278/278
In invalidate and flush functions of eDP DRRS, if deferred downclock
work starts execution at a time window between acquiring the drrs
mutex and cancellation of the deferred work
(intel_edp_drrs_downclock_work), then deferred work will find
drrs mutex locked and wait for the same.
Meanwhile the fu
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5861
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -4 278/278
On 3/2/2015 9:49 PM, Damien Lespiau wrote:
This translation entry was updated after electrical validation by the hw
team. The other entries are removed from existence as they aren't
validated and because the sole use of a certain type of level shifter
for SKL products is anticipated.
v2: Remov
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5853
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 278/278
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5849
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -9 278/278
On Fri, Feb 27, 2015 at 10:12:14PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 27, 2015 at 12:12:28PM -0800, jeff.mc...@intel.com wrote:
> > From: Jeff McGee
> >
> > Total EU was already being detected on CHV, so we just add the
> > additional info parameters. The detection method is changed to
> >
On Mon, Mar 02, 2015 at 03:37:32PM -0800, jeff.mc...@intel.com wrote:
> From: Jeff McGee
>
> Setup new I915_GETPARAM ioctl entries for subslice total and
> EU total. Userspace drivers need these values when constructing
> GPGPU commands. This kernel query method is intended to replace
> the PCI I
From: Jeff McGee
We need to update some fields of the device's cl_device_id
struct at runtime using driver-specific methods. It is best to
group all such updates into a single driver callback to avoid
opening/initing and deiniting/closing the device multiple times.
Signed-off-by: Jeff McGee
---
From: Jeff McGee
Values of device max compute units and max subslice obtained
directly from the driver should be more accurate than our own
ID-based lookup values. This is particularly important when a
single device ID may encompass more than one configuration. If
the driver cannot provide a vali
From: Jeff McGee
New test core_getparams consists of 2 subtests, each one testing
the ability of userspace to query the correct value of a GT config
attribute: subslice total or EU total. drm/i915 implementation of
these queries is required for Cherryview and Gen9+ devices (non-
simulated).
For:
From: Jeff McGee
Update kernel interface with new I915_GETPARAM ioctl entries for
subslice total and EU total. Add a wrapping function for each
parameter. Userspace drivers need these values when constructing
GPGPU commands. This kernel query method is intended to replace
the PCI ID-based tables
From: Jeff McGee
Setup new I915_GETPARAM ioctl entries for subslice total and
EU total. Userspace drivers need these values when constructing
GPGPU commands. This kernel query method is intended to replace
the PCI ID-based tables that userspace drivers currently maintain.
The kernel driver can em
On Mon, Mar 2, 2015 at 3:41 AM, Jindal, Sonika wrote:
>
>
> On 2/28/2015 6:56 AM, Rodrigo Vivi wrote:
>>
>> On Haswell and Broadwell with link in standby when exit event happens
>> between vblank and VSC packet, PSR exit on panel but DPA transmitter
>> still sends black pixel. hen this condition h
On Mon, 2015-03-02 at 20:44 +0200, Ville Syrjälä wrote:
> On Mon, Mar 02, 2015 at 07:07:47PM +0100, Daniel Vetter wrote:
> > On Mon, Mar 02, 2015 at 11:33:39AM -0500, Brian J. Murrell wrote:
> > >
> > > [ 50.508381] [drm:drm_mode_debug_printmodeline] Modeline 27:"1600x1200"
> > > 0 202500 1600
On Mon, 2015-03-02 at 19:07 +0100, Daniel Vetter wrote:
> On Mon, Mar 02, 2015 at 11:33:39AM -0500, Brian J. Murrell wrote:
> > On Mon, 2015-03-02 at 09:07 +, Chris Wilson wrote:
> >
> > > Can you please attach dmesg with drm.debug=6 on the command line?
> >
> > Please find it attached. I di
2015-02-24 1:55 GMT+02:00 Marc Finet :
> On Sun, Feb 22, 2015 at 11:38:36AM +0100, Daniel Vetter wrote:
>> In
>>
>> daniel@phenom:~/linux/src$ git show ccfc08655
>> commit ccfc08655d5fd5076828f45fb09194c070f2f63a
>> Author: Rob Clark
>> Date: Thu Dec 18 16:01:48 2014 -0500
>>
>> drm: tweak g
I think your ilk_wm_method2 is busted. Method 2 should always give more than
one full line, making this 1 line redundant.
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
Sent: Monday, March 02, 2015 9:09 AM
To: Intel Graphics Development; Runyan, Arthur J
Cc: Dan
2015-02-25 10:34 GMT-03:00 Mika Kuoppala :
> Michel Thierry writes:
>
>> From: Ben Widawsky
>>
>> As we move toward dynamic page table allocation, it becomes much easier
>> to manage our data structures if break do things less coarsely by
>> breaking up all of our actions into individual tasks.
2015-03-02 15:20 GMT-03:00 Damien Lespiau :
> I was dumping the DDI translation tables to make sure my patch updating
> the HDMI entry was doing the right thing when I noticed that the table
> was showing reset values after DPMS.
>
> And indeed, the DDI translation registers are in power well 1 on
On Mon, Mar 02, 2015 at 07:07:47PM +0100, Daniel Vetter wrote:
> On Mon, Mar 02, 2015 at 11:33:39AM -0500, Brian J. Murrell wrote:
> > On Mon, 2015-03-02 at 09:07 +, Chris Wilson wrote:
> >
> > > Can you please attach dmesg with drm.debug=6 on the command line?
> >
> > Please find it attached
2015-02-13 17:37 GMT-02:00 Damien Lespiau :
> We don't use this function on gen9, no need for that test here.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/dri
2015-02-13 17:37 GMT-02:00 Damien Lespiau :
> The pipe interrupt registers are in the actual pipe power well, so we
> need to restore them when re-enable the corresponding power well.
>
> I've also copied what we do on HSW/BDW for VGA, even if the we haven't
> enabled unclaimed registers just yet.
On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote:
> On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
> > There are some cases like suspend/resume or dpms off/on sequences
> > that can flush frontbuffer bits. In these cases features that relies
> > on frontbuffer tracking can star
2015-02-13 17:37 GMT-02:00 Damien Lespiau :
> While we only need to restore pipe B/C interrupt registers on BDW when
> enabling the power well, skylake a bit more flexible and we'll also need
> to restore the pipe A registers as it has its own power well that can be
> toggled.
- I'll admit I had t
On Mon, Mar 02, 2015 at 03:33:27PM +, tim.g...@intel.com wrote:
> From: Tim Gore
>
> The gem_render_linear_blits test tends to get oom killed
> on low memory (< 4GB) Android systems. This is because the
> test tries to allocate (sysinfo.totalram * 9 / 10) in
> buffer objects and the remaining
I was dumping the DDI translation tables to make sure my patch updating
the HDMI entry was doing the right thing when I noticed that the table
was showing reset values after DPMS.
And indeed, the DDI translation registers are in power well 1 on SKL,
and so we're losing their values when shutting d
The commit message explains it all, but this cover letter can be made somewhat
useful by saying this patch is on top of:
http://lists.freedesktop.org/archives/intel-gfx/2015-February/060079.html
--
Damien
Damien Lespiau (1):
drm/i915/skl: Restore the DDI translation tables when enabling PW1
On Mon, Mar 02, 2015 at 02:43:50PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> 90/270 rotated scanout needs a rotated GTT view of the framebuffer.
>
> This is put in a separate VMA with a dedicated ggtt_view and wired suchs that
> it is created when a framebuffer is pinned to a 90/27
On 02/03/2015 17:43, Daniel Vetter wrote:
On Mon, Mar 02, 2015 at 11:07:20AM +, Arun Siluvery wrote:
Some of the workarounds are to be applied during context save but before
restore and some at the end of context save/restore but before executing
the instructions in the ring. Workaround batc
From: Ville Syrjälä
The specs seem to be full of misinformation wrt. the Punit register
0x36. Some versions still show the old VLV bit layout, some the new
layout, and all of them seem to tell us nonsense about the cdclk
value encoding.
Testing on actual hardware has shown that we simply need to
From: Ville Syrjälä
Supposedly CHV can sustain a pixel clock of up to 95% of
cdclk, as opposed to the 90% limit that was used old older
platforms. Update the cdclk selection code to allow for this.
This will allow eg. HDMI 4k modes with their 297MHz pixel clock
while still respecting the 320 MHz
On Sat, Feb 28, 2015 at 02:54:09PM +, Damien Lespiau wrote:
> Implicit usage of local variables in macros isn't exactly the greatest
> thing in the world, especially when that variable is the drm device and
> we want to move towards a broader use of the i915 device structure.
>
> Let's make fo
On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
> There are some cases like suspend/resume or dpms off/on sequences
> that can flush frontbuffer bits. In these cases features that relies
> on frontbuffer tracking can start working and user can stop getting
> screen updates on fbcon ha
On Fri, Feb 27, 2015 at 08:26:01PM -0500, Rodrigo Vivi wrote:
> This wrong logic and useless define came from first versions and
> came along with all rework. Just now I notice how ugly, wrong and
> useless this is.
>
> val is already defined as 0 anyway and logic is completelly wrong
> and useles
On Fri, Feb 27, 2015 at 05:25:52PM -0800, Chandra Konduru wrote:
> From: chandra konduru
>
> Adding i-g-t test case to test display crtc background color.
>
> v2:
> - Added IGT_TEST_DESCRIPTION() (Thomas Wood)
> - Added to .gitignore (Thomas Wood)
> - Added additional details to function header
On Fri, Feb 27, 2015 at 08:51:39PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 27, 2015 at 07:47:46PM +0100, Daniel Vetter wrote:
> > On Fri, Feb 27, 2015 at 08:21:07PM +0200, Ville Syrjälä wrote:
> > > On Fri, Feb 27, 2015 at 08:54:19AM -0800, Matt Roper wrote:
> > > > Move watermark handling from i
On Mon, Mar 02, 2015 at 11:07:20AM +, Arun Siluvery wrote:
> Some of the workarounds are to be applied during context save but before
> restore and some at the end of context save/restore but before executing
> the instructions in the ring. Workaround batch buffers are created for
> this purpos
On Mon, Mar 2, 2015 at 5:53 PM, Linus Torvalds
wrote:
> On Mon, Mar 2, 2015 at 1:04 AM, Daniel Vetter wrote:
>> And can you please attach a bactrace of the WARN in your patch, just to
>> double-check you blow up at the same spot?
>
> So the dmesg I attached had a backtrace for the new WARN_ONCE()
On Mon, Mar 02, 2015 at 04:49:31PM +0200, Ville Syrjälä wrote:
> On Mon, Mar 02, 2015 at 03:44:58PM +0100, Daniel Vetter wrote:
> > On Fri, Feb 27, 2015 at 08:09:20PM +0200, Ville Syrjälä wrote:
> > > Actually this is going to have issues now that atomic is partially in.
> > > We'd need to look at
Forgotten to cc Art as fyi.
-Daniel
On Mon, Mar 2, 2015 at 5:35 PM, Daniel Vetter wrote:
> My snb seemed somewhat unhappy with 256x256 cursors and failed all the
> relevant kms_cursor_crc subtests sporadically, including logging cpu
> fifo underruns. Smaller cursor work perfectly with a failure r
My snb seemed somewhat unhappy with 256x256 cursors and failed all the
relevant kms_cursor_crc subtests sporadically, including logging cpu
fifo underruns. Smaller cursor work perfectly with a failure rate at
least 1000x less (got bored after running tests for days).
After some playing around with
From: Tim Gore
The gem_render_tiled_blits test tends to get oom killed
on low memory (< 4GB) Android systems. This is because the
test tries to allocate (sysinfo.totalram * 9 / 10) in
buffer objects and the remaining 10% of memory is not
always enough for the Android system.
A similar issue with
On Mon, Mar 2, 2015 at 1:04 AM, Daniel Vetter wrote:
>
> And can you please attach a bactrace of the WARN in your patch, just to
> double-check you blow up at the same spot?
So the dmesg I attached had a backtrace for the new WARN_ONCE() (in
addition to an unrelated(?) one from i915_gem_free_obje
On Mon, 2015-03-02 at 14:27 +, Chris Wilson wrote:
> On Mon, Mar 02, 2015 at 09:07:10AM -0500, Brian J. Murrell wrote:
> > On Mon, 2015-03-02 at 13:37 +, Chris Wilson wrote:
> > >
> > > Definitely, currently we have no idea even what hardware you are
> > > using... Could you please attach
This translation entry was updated after electrical validation by the hw
team. The other entries are removed from existence as they aren't
validated and because the sole use of a certain type of level shifter
for SKL products is anticipated.
v2: Remove all the other entries and force the use of th
On Mon, Mar 02, 2015 at 02:43:48PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Use cases like rotation require these hooks to have some context so they
> know how to prepare and cleanup the frame buffer correctly.
>
> For i915 specifically, object backing pages need to be mapped diff
From: Tim Gore
The gem_render_linear_blits test tends to get oom killed
on low memory (< 4GB) Android systems. This is because the
test tries to allocate (sysinfo.totalram * 9 / 10) in
buffer objects and the remaining 10% of memory is not
always enough for the Android system.
After a discussion w
This reverts commit 3f678c96abb43a977d2ea41aefccdc49e8a3e896.
We've been a bit too optimistic with this one here :(
The trouble is that internally we're still using these plane
update/disable hooks. Which was totally ok pre-atomic since the drm
core did all the book-keeping updating and these jus
On Fri, Feb 27, 2015 at 01:54:02PM -0800, Rodrigo Vivi wrote:
> cool, thanks for the detailed explanation.
> Reviewed-by: Rodrigo Vivi
Queued for -next, thanks for the patch.
-Daniel
>
> On Fri, Feb 27, 2015 at 6:04 AM, Daniel Vetter wrote:
> > On Thu, Feb 26, 2015 at 05:11:16PM -0800, Rodrigo
On Mon, Mar 02, 2015 at 03:44:58PM +0100, Daniel Vetter wrote:
> On Fri, Feb 27, 2015 at 08:09:20PM +0200, Ville Syrjälä wrote:
> > On Fri, Feb 27, 2015 at 09:57:20AM -0800, Jesse Barnes wrote:
> > > On 02/10/2015 05:28 AM, ville.syrj...@linux.intel.com wrote:
> > > > From: Ville Syrjälä
> > > >
From: Tvrtko Ursulin
Display engine on Skylake can scan out specially prepared frame buffers
rotated by 90 or 270 degrees.
This adds partial support for that - display programming patches are missing
from this initial posting because for now the only purpose is to see if people
now like the appr
On Fri, Feb 27, 2015 at 08:09:20PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 27, 2015 at 09:57:20AM -0800, Jesse Barnes wrote:
> > On 02/10/2015 05:28 AM, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä
> > >
> > > Now that we have drm_planes for the cursor and primary we can move
From: Tvrtko Ursulin
Need to do this in order to support 90/270 rotated display.
v2: Pass in drm_plane instead of plane index to intel_obj_display_address.
v3:
* Renamed intel_obj_display_address to intel_plane_obj_offset.
(Chris Wilson)
* Simplified rotation check to bitwise AND.
From: Tvrtko Ursulin
90/270 rotated scanout needs a rotated GTT view of the framebuffer.
This is put in a separate VMA with a dedicated ggtt_view and wired suchs that
it is created when a framebuffer is pinned to a 90/270 rotated plane.
Rotation is only possible with Yb/Yf buffers and error is
From: Tvrtko Ursulin
Use cases like rotation require these hooks to have some context so they
know how to prepare and cleanup the frame buffer correctly.
For i915 specifically, object backing pages need to be mapped differently
for different rotation modes and the driver needs to know which mapp
From: Tvrtko Ursulin
v2: Pass in rotation info to sprite plane updates as well.
v3: Use helper to determine 90/270 rotation. (Michel Thierry)
v4: Rebased for fb modifiers and atomic changes.
For: VIZ-4546
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry (v3)
---
drivers/gpu/drm/i91
From: Tvrtko Ursulin
It will be used in a later patch.
v2: Rebased for fb modifiers.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_display.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i
On Mon, Mar 02, 2015 at 09:07:10AM -0500, Brian J. Murrell wrote:
> On Mon, 2015-03-02 at 13:37 +, Chris Wilson wrote:
> >
> > Definitely, currently we have no idea even what hardware you are
> > using... Could you please attach Xorg.0.log
>
> Please find it attached.
>
> > or whatever incom
On Mon, 2015-03-02 at 13:37 +, Chris Wilson wrote:
>
> Definitely, currently we have no idea even what hardware you are
> using... Could you please attach Xorg.0.log
Please find it attached.
> or whatever incompleteness
> passes for that after journald?
Hrm. Not sure what this means. Hope
On Sat, Feb 28, 2015 at 09:04:44PM +, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index e07a1cb..c204e30 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -223,8 +223,10 @@ enum h
On Mon, Mar 02, 2015 at 07:44:22AM -0500, Brian J. Murrell wrote:
> I have noticed something strange on my Fedora 21 with i915. If I am
> using something that utilizes vaapi, like VLC for instance, the screen
> only refreshes on mouse movements.
>
> This becomes abundantly clear when I watch the
Jani Nikula writes:
> On Mon, 02 Mar 2015, Imre Deak wrote:
>> Bjørn reported that his machine hang during hibernation and eventually
>> bisected the problem to the following commit:
>>
>> commit da2bc1b9db3351addd293e5b82757efe1f77ed1d
>> Author: Imre Deak
>> Date: Thu Oct 23 19:23:26 2014 +
I have noticed something strange on my Fedora 21 with i915. If I am
using something that utilizes vaapi, like VLC for instance, the screen
only refreshes on mouse movements.
This becomes abundantly clear when I watch the clock on my panel for
example, which displays seconds on it. It will sit at
On Mon, 02 Mar 2015, Imre Deak wrote:
> Bjørn reported that his machine hang during hibernation and eventually
> bisected the problem to the following commit:
>
> commit da2bc1b9db3351addd293e5b82757efe1f77ed1d
> Author: Imre Deak
> Date: Thu Oct 23 19:23:26 2014 +0300
>
> drm/i915: add pow
On 2/28/2015 6:56 AM, Rodrigo Vivi wrote:
On Haswell and Broadwell with link in standby when exit event happens
between vblank and VSC packet, PSR exit on panel but DPA transmitter
still sends black pixel. hen this condition hits, panel will intermittently
display black frame.
The known W/A fo
On Mon, 2015-03-02 at 09:07 +, Chris Wilson wrote:
>
> Gut feeling is that this is related to HDMIv1.2 versus later.
I should have mentioned, the monitor that is not getting it's
1600x1200@75Hz timing picked up is on the D-Sub connector, not HDMI.
> For reference the loop in pipe is bug 8534
On 02/03/2015 11:02, Arun Siluvery wrote:
Please ignore this one. I used message id of cover letter instead of v1
of this patch. Latest patches are sent in reply to their initial revisions.
regards
Arun
From: Namrta
This can be used to enable WA BB infrastructure for features like
RC6, SSE
Some of the workarounds are to be applied during context save but before
restore and some at the end of context save/restore but before executing
the instructions in the ring. Workaround batch buffers are created for
this purpose as they cannot be applied using normal means. HW executes
them at spe
From: Namrta
This can be used to enable WA BB infrastructure for features like
RC6, SSEU and in between context save/restore etc.
The patch which would need WA BB will have to declare the wa_bb obj
utilizing the function here. Update the WA BB with required commands
and update the address of the
Bjørn reported that his machine hang during hibernation and eventually
bisected the problem to the following commit:
commit da2bc1b9db3351addd293e5b82757efe1f77ed1d
Author: Imre Deak
Date: Thu Oct 23 19:23:26 2014 +0300
drm/i915: add poweroff_late handler
The problem seems to be that afte
From: Namrta
This can be used to enable WA BB infrastructure for features like
RC6, SSEU and in between context save/restore etc.
The patch which would need WA BB will have to declare the wa_bb obj
utilizing the function here. Update the WA BB with required commands
and update the address of the
On CHT, changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct dividor
& ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.
Signed-off-by: Gaurav K Singh
---
drivers/g
On Mon, Mar 02, 2015 at 10:44:16AM +0100, Paul Bolle wrote:
> On Sat, 2015-02-28 at 22:08 -0800, Linus Torvalds wrote:
> > Hmm. 3.19 works fine, even if it ends up spewing
> >
> > WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/drm_irq.c:1121
> > drm_wait_one_vblank+0x125/0x130()
> > vblank not
On Mon, 02 Mar 2015, Paul Bolle wrote:
> On Sat, 2015-02-28 at 22:08 -0800, Linus Torvalds wrote:
>> Hmm. 3.19 works fine, even if it ends up spewing
>>
>> WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/drm_irq.c:1121
>> drm_wait_one_vblank+0x125/0x130()
>> vblank not available on crtc 1, ret=
On 02/03/2015 10:10, Michel Thierry wrote:
On 25/02/15 17:54, Arun Siluvery wrote:
Some of the workarounds are to be applied during context save but before
restore and some at the end of context save/restore but before executing
the instructions in the ring. Workaround batch buffers are create
On 25/02/15 17:54, Arun Siluvery wrote:
Some of the workarounds are to be applied during context save but before
restore and some at the end of context save/restore but before executing
the instructions in the ring. Workaround batch buffers are created for
this purpose as they cannot be applied
On Sat, 2015-02-28 at 22:08 -0800, Linus Torvalds wrote:
> Hmm. 3.19 works fine, even if it ends up spewing
>
> WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/drm_irq.c:1121
> drm_wait_one_vblank+0x125/0x130()
> vblank not available on crtc 1, ret=-22
>
> a lot.
For what it's worth, that stre
From: Ville Syrjälä
Apparently we must yet halve the DDL drain latency from what we're
using currently. This little nugget is not in any spec, but came
down through the grapevine.
This makes the displays a bit more stable. Not quite fully stable but at
least they don't fall over immediately o
Stable team, please backport
commit f9b61ff6bce9a44555324b29e593fdffc9a115bc
Author: Daniel Vetter
Date: Wed Jan 7 13:54:39 2015 +0100
drm/i915: Push vblank enable/disable past encoder->enable/disable
to 3.19.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89108
Quite likely al
On Sun, Mar 01, 2015 at 02:12:16PM -0500, Brian J. Murrell wrote:
> I have a dual-head set up here which I've recently changed the
> motherboard out and with it, removed an nVidia GT210 and replaced it
> with the on-board graphics that came on this:
>
> CPU: Intel(R) Celeron(R) CPU G1840 @ 2.80GHz
On Sat, Feb 28, 2015 at 05:20:41PM +0100, Yannick Guerrini wrote:
> Change 'mutliple' to 'multiple'
> Change 'mutlipler' to 'multiplier'
> Change 'Haswel' to 'Haswell'
>
> Signed-off-by: Yannick Guerrini
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_gem_exec
On Sun, Mar 01, 2015 at 05:59:53PM -0800, Linus Torvalds wrote:
> On Sun, Mar 1, 2015 at 1:00 PM, Linus Torvalds
> wrote:
> >
> > Back to the drawing board.
>
> Ok, many hours later, but I found it.
>
> The bisection was a disaster, having to work around other bugs in this
> area, but it ended u
On Fri, Feb 27, 2015 at 08:23:41PM +0200, Imre Deak wrote:
> We've checked today with Ville a few machines we've found from GEN2 to
> GEN5+. There was one Thinkpad x61s (GEN4) where I could reproduce the
> exact same problem and get rid of it using the same workaround. All the
> others were non-Len
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