v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros
(Ville)
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_dp.c | 28 ++--
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/
v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh).
v3: Reading dpcd's supported link rates tables based upon edp version in the
same patch.
v4: Move version check under is_edp (Satheesh)
v5: Using le16 for rates, some naming, and removing nested if block (Ville)
v6: Corre
eDp 1.4 supports custom frequencies.
Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and
4.32 GHz along with usual LBR, HBR and HBR2 frequencies.
Read sink supported frequencies and get common frequencies from sink and
source and use these for link training.
v2: Rebased, r
This series adds support for edp1.4 intermediate frequencies supported by
Skylake
This addresses review comments by Ville and some reformatting.
Sonika Jindal (4):
drm: Adding edp1.4 specific dpcd macros
drm/i915/skl: Read sink supported rates from edp panel
drm/i915/skl: Add support for ed
Adding dpcd macros related to edp1.4 and link rates
v2: Added DP_SUPPORTED_LINK_RATES macros
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Sonika Jindal
Reviewed-by: Todd Previte
---
include/drm/drm_dp_helper.h |8
1 file changed, 8 insertions(+)
diff --git a/include/drm/drm
Updating recommended DDI translation table for edp 1.4
as per bspec update
Signed-off-by: Sonika Jindal
Reviewed-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_ddi.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/dr
From: chandra konduru
Adding i-g-t test case to test display crtc background color.
Signed-off-by: chandra konduru
---
lib/igt_kms.c | 60 +++
lib/igt_kms.h | 4 +
tests/Android.mk | 1 +
tests/Makefile.sources|
This patch adds support for Skylake display pipe background color.
v2:
- added property documentation to drm DocBook (Daniel Vetter)
- moved property to drm_mode_config (Daniel Vetter)
- change to set property to NULL once it is freed. (me)
- change to make sure gamma/csc settings were retained du
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5801
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 277/277
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 02/11/2015 05:02 AM, Daniel Vetter wrote:
> On Wed, Feb 11, 2015 at 1:55 AM, Sean V Kelley
> wrote:
>> No corruption seen. I will add reloc domains to my growing audit
>> list.
>
> One more for the libva audit list:
>
> If you do any ioctl dir
On Fri, 2015-02-20 at 19:40 +, Chris Wilson wrote:
> On Fri, Feb 20, 2015 at 09:09:02PM +0200, Imre Deak wrote:
> > +static void intel_irq_set_state(struct drm_i915_private *dev_priv,
> > + bool enabled)
> > +{
> > + dev_priv->pm.irqs_enabled = enabled;
> > + /*
>
On Fri, Feb 20, 2015 at 09:09:02PM +0200, Imre Deak wrote:
> +static void intel_irq_set_state(struct drm_i915_private *dev_priv,
> + bool enabled)
> +{
> + dev_priv->pm.irqs_enabled = enabled;
> + /*
> + * Before we unmask the interrupt or synchronize agains
Atm, it's possible that the interrupt handler is called when the device
is in D3 or some other low-power state. It can be due to another device
that is still in D0 state and shares the interrupt line with i915, or on
some platforms there could be spurious interrupts even without sharing
the interru
On Thu, Feb 19, 2015 at 10:15 PM, Ramalingam C wrote:
> Hi,
>
>
> On Thursday 19 February 2015 10:55 PM, Rodrigo Vivi wrote:
>>
>> On Fri, Feb 13, 2015 at 2:03 AM, Ramalingam C
>> wrote:
>>>
>>> From: Vandana Kannan
>>>
>>> For Broadwell, there is one instance of Transcoder MN values per
>>> tra
From: Ben Widawsky
Map is easy, it's the same register as the PDP descriptor 0, but it only
has one entry.
v2: PML4 update in legacy context switch is left for historic reasons,
the preferred mode of operation is with lrc context based submission.
Signed-off-by: Ben Widawsky
Signed-off-by: Mic
From: Ben Widawsky
Note that there is no gen8 ppgtt debug_dump function yet.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 32
drivers/gpu/drm/i
From: Ben Widawsky
The code for 4lvl works just as one would expect, and nicely it is able
to call into the existing 3lvl page table code to handle all of the
lower levels.
PML4 has no special attributes, and there will always be a PML4.
So simply initialize it at creation, and destroy it at the
These patches rely on "PPGTT dynamic page allocations", currently under review,
to provide GEN8 dynamic page table support with 64b addresses. As the review
progresses, these patches may be combined.
In order expand the GPU address space, a 4th level translation is added, the
Page Map Level 4 (PML
From: Ben Widawsky
v2: 0 pad the new 8B fields or else intel_error_decode has a hard time.
Note, regardless we need an igt update.
v3: Make reloc_offset 64b also.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i9
From: Ben Widawsky
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b address space a bit
easier to swallow. The patch also introduces the PML4, ie. the new top
level structure of the page tables.
v2: Renamed pdp_free to b
From: Ben Widawsky
As a step towards implementing 4 levels, while not discarding the
existing pte map functions, we need to pass the sg_iter through. The
current function understands to the page directory granularity. An
object's pages may span the page directory, and so using the iter
directly a
From: Ben Widawsky
The dynamic page allocation patch series added it for GEN6, this patch
adds them for GEN8.
v2: Consolidate pagetable/page_directory events
v3: Multiple rebases.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v3)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 23
Use 48b addresses if hw supports it and i915.enable_ppgtt=3.
Aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++-
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu
When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map
Level 4 (PML4), before it selects which Page Directory Pointer (PDP)
it will write to.
Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range.
Also add a scratch page for PML4.
This patch was inspired by B
From: Ben Widawsky
The insert_entries function was the function used to write PTEs. For the
PPGTT it was "hardcoded" to only understand two level page tables, which
was the case for GEN7. We can reuse this for 4 level page tables, and
remove the concept of insert_entries, which was never viable p
From: Ben Widawsky
Up until now, ppgtt->pdp has always been the root of our page tables.
Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs.
In preparation for 4 level page tables, we need to stop use ppgtt->pdp
directly unless we know it's what we want. The future structure will use
ppgt
In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains
the base address to PML4, while the other PDP registers are ignored.
Also, the addressing mode must be specified in every context descriptor.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 167 ++
On 2/20/2015 1:25 AM, Jani Nikula wrote:
On Thu, 19 Feb 2015, Todd Previte wrote:
Just some formatting issues that need to be cleaned up. Otherwise the
definitions look correct according to the eDP 1.4 spec.
Actually the formatting seems to be in line with the rest of that
particular file.
B
Readding intel-gfx.
On Wed, Feb 18, 2015 at 5:57 PM, Todd Previte wrote:
> On 12/17/14 1:20 PM, Daniel Vetter wrote:
>> Just something random I've spotted while driving by: drm_get_edid does all
>> the checksum stuff for you already (it retries up to 4 times if the
>> checkusm is off and also che
Michel Thierry writes:
> From: Ben Widawsky
>
> As we move toward dynamic page table allocation, it becomes much easier
> to manage our data structures if break do things less coarsely by
> breaking up all of our actions into individual tasks. This makes the
> code easier to write, read, and ve
Michel Thierry writes:
> From: Ben Widawsky
>
> Instead of implementing the full tracking + dynamic allocation, this
> patch does a bit less than half of the work, by tracking and warning on
> unexpected conditions. The tracking itself follows which PTEs within a
> page table are currently being
Hi,
On Friday 20 February 2015 12:15 AM, Rodrigo Vivi wrote:
On Fri, Feb 13, 2015 at 2:03 AM, Ramalingam C wrote:
From: Vandana Kannan
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5799
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 277/277
At first glance, this is interesting. On reflection I think I still only
care about the register values at the time of the error. Otherwise, I
would rather have the last few registers written - and only those of the
interesting set as defined by the error state - their values and when.
We would als
On Fri, Feb 20, 2015 at 09:55:09AM -0200, Paulo Zanoni wrote:
> 2015-02-20 3:33 GMT-02:00 Ben Widawsky :
> > Register writes are supposed to be posted, and therefore "fast." In order
> > to try
> > to preserve this behavior, the patch uses percpu variables to make the
> > overhead
> > minimal. Th
2015-02-20 3:33 GMT-02:00 Ben Widawsky :
> Register writes are supposed to be posted, and therefore "fast." In order to
> try
> to preserve this behavior, the patch uses percpu variables to make the
> overhead
> minimal. The slow data collection is done at error time, and that only occurs
> if
>
Dave Gordon writes:
> When querying the GTFIFOCTL register to check the FIFO space, the read value
> must be masked. The operation is repeated explicitly in several places. This
> change refactors the read-and-mask code into a function call.
>
> v2: rebased on top of Mika's forcewake patch set, s
John Harrison writes:
> Please note that a lot of the issues with _i915_add_request are cleaned
> up by my patch series to remove the outstanding_lazy_request. The add to
> client in some random client context is fixed, the messy execlist vs
> legacy ringbuf decisions are removed, the execlist
On Thu, 19 Feb 2015, Todd Previte wrote:
> Just some formatting issues that need to be cleaned up. Otherwise the
> definitions look correct according to the eDP 1.4 spec.
Actually the formatting seems to be in line with the rest of that
particular file.
BR,
Jani.
>
> -T
>
> On 2/19/15 12:46 AM
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