Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->284/291
PNV: pass/total=356/356->350
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->290/291
PNV: pass/total=356/356->356
On Wed, 12 Nov 2014, Daniel Vetter wrote:
> On Wed, Nov 12, 2014 at 05:01:10PM +0200, Jani Nikula wrote:
>> Use the same conditions, group by features, add comments.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_suspend.c | 18 +-
>> 1 file changed, 9 inse
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->284/291
PNV: pass/total=356/356->350
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->290/291
PNV: pass/total=356/356->356
Hi, All
As you may already noticed that, patches for kernel sent to this
intel-gfx mailing list is automatically picked up for testing.
Test Reports that covered 7 intel platforms are replied to the patches.
At the moment, this functionality only covers patches sent by Intel Engineers
If
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->291/291
PNV: pass/total=356/356->350
From: Ville Syrjälä
Currently it's possible to get visible cache dirt on scanout on LLC
machines when using pwrite on the future scanout bo if its cache_level
is already NONE.
pwrite's "does this need clflush?" checks would decide that no clflush
is necessary since the bo isn't currently pinned
This has been invalidated in
commit 24f3a8cf7766e52a087904b4346794c7b410f957
Author: Akash Goel
Date: Tue Jun 17 10:59:42 2014 +0530
drm/i915: Added write-enable pte bit supportt
But despite that it's in the diff context no one noticed :(
Cc: Akash Goel
Cc: Imre Deak
Signed-off-by: Dan
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->290/291
PNV: pass/total=356/356->356
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->291/291
PNV: pass/total=356/356->356
From: gsarora
Added Android.mk for intel_sprite_on.
v2: Addressed review comments by Daniel Vetter.
- Moved the cairo independent functions from igt_kms.c to igt_aux.c.
Signed-off-by: Gagandeep S Arora
---
Android.mk | 2 +-
demos/Android.mk | 27 +
lib/igt_
On Wed, Nov 12, 2014 at 9:37 AM, Daniel Vetter wrote:
> On Mon, Nov 10, 2014 at 02:56:50PM +, Robert Bragg wrote:
> > This adds i915_gem_context_pin/unpin_state functions so that code
> > outside i915_gem_context.c can pin/unpin a context without duplicating
> > knowledge about the alignment
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=247/348->276/348
PNV: pass/total=326/328->324
On Thu, Nov 06, 2014 at 02:39:25PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Things like reliable GGTT mmaps and mirrored 2d-on-3d display will need
> to map objects into the same address space multiple times.
>
> This also means that objects now can have multiple VMA entries.
>
>
On Wed, Nov 12, 2014 at 05:33:08PM +0100, Daniel Vetter wrote:
> On Wed, Nov 12, 2014 at 10:46 AM, Chris Wilson
> wrote:
> > On Wed, Nov 12, 2014 at 09:44:34AM +0100, Daniel Vetter wrote:
> >> On Fri, Nov 07, 2014 at 02:22:01PM -0800, bradley.d.vol...@intel.com wrote:
> >> > + if (obj &
On Wed, Nov 12, 2014 at 10:46 AM, Chris Wilson wrote:
> On Wed, Nov 12, 2014 at 09:44:34AM +0100, Daniel Vetter wrote:
>> On Fri, Nov 07, 2014 at 02:22:01PM -0800, bradley.d.vol...@intel.com wrote:
>> > + if (obj && obj->madv == __I915_MADV_PURGED) {
>> > + was_purged =
On Wed, Nov 12, 2014 at 08:00:26AM -0800, Rodrigo Vivi wrote:
> I believe that on docs that is visible to end users we could use more
> market names besides the codenames.
This isn't documentation for end users but developers working on i915. So
aligning with the codenames used in the driver is mo
On Wed, Nov 12, 2014 at 1:16 AM, Daniel Vetter wrote:
> On Fri, Nov 07, 2014 at 03:55:18PM -0800, Rodrigo Vivi wrote:
>> Let's document PSR a bit. No functional changes.
>>
>> Signed-off-by: Rodrigo Vivi
>
> I've tried to merge the preceeding patches to avoid rebase pain, but
> there's conflicts.
On Wed, Nov 12, 2014 at 05:01:10PM +0200, Jani Nikula wrote:
> Use the same conditions, group by features, add comments.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_suspend.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=247/348->277/348
PNV: pass/total=326/328->323
On Wed, Nov 12, 2014 at 02:48:52PM +0200, Jani Nikula wrote:
> The block was added for spin_lock_irqsave flags, but since the locking
> was converted to spin_lock_irq variant, the block is no longer needed.
>
> Signed-off-by: Jani Nikula
Queued for -next, thanks for the patch.
-Daniel
--
Daniel
On Wed, Nov 12, 2014 at 04:40:35PM +0200, Imre Deak wrote:
> Without this RPM ref we can hit the device suspended WARN via:
> i915_gem_object_pin()->ggtt_bind_vma->gen6_ggtt_insert_entries(). I
> noticed this on my BYT while keeping the i915 device in runtime
> suspended state for a while. I chose
On Wed, Nov 12, 2014 at 04:57:10PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Currently it's possible to get visible cache dirt on scanout on LLC
> machines when using pwrite on the future scanout bo if its cache_level
> is already NONE.
>
> pwrite's "does this need cl
On Wed, Nov 12, 2014 at 03:01:30PM +, Chris Wilson wrote:
> On Wed, Nov 12, 2014 at 04:57:10PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Currently it's possible to get visible cache dirt on scanout on LLC
> > machines when using pwrite on the future scanout b
On Wed, Nov 12, 2014 at 04:57:10PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Currently it's possible to get visible cache dirt on scanout on LLC
> machines when using pwrite on the future scanout bo if its cache_level
> is already NONE.
>
> pwrite's "does this need cl
Use the same conditions, group by features, add comments.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_suspend.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c
b/drivers/gpu/drm/i915/i915_suspend.c
index 3c1
From: Ville Syrjälä
Currently it's possible to get visible cache dirt on scanout on LLC
machines when using pwrite on the future scanout bo if its cache_level
is already NONE.
pwrite's "does this need clflush?" checks would decide that no clflush
is necessary since the bo isn't currently pinned
On Wed, Nov 12, 2014 at 03:22:07PM +0100, Daniel Vetter wrote:
> On Wed, Nov 12, 2014 at 01:49:47PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 11, 2014 at 10:30:57AM +0100, Daniel Vetter wrote:
> > > On Mon, Nov 10, 2014 at 07:15:04PM +0200, Ville Syrjälä wrote:
> > > > As a side note if someone i
Without this RPM ref we can hit the device suspended WARN via:
i915_gem_object_pin()->ggtt_bind_vma->gen6_ggtt_insert_entries(). I
noticed this on my BYT while keeping the i915 device in runtime
suspended state for a while. I chose this place to take the ref to
avoid the possible deadlock via the m
This is not used within the driver, and merely saving/restoring these
registers isn't going to do any good anyway. In fact, it's possible it's
actively harmful. Any code enabling the feature should handle this
completely in the regular platform specific enable/disable backlight
functions.
Signed-o
AFAICT i9xx_pfit_disable() on the GMCH display crtc disable path in
i9xx_crtc_disable() will always disable the panel fitter by writing 0 to
PFIT_CONTROL. The register save will always save/restore 0.
Move the PFIT_CONTROL and PFIT_PGM_RATIOS save/restore to UMS
code. While at it, save/restore the
On Wed, Nov 12, 2014 at 01:49:47PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 11, 2014 at 10:30:57AM +0100, Daniel Vetter wrote:
> > On Mon, Nov 10, 2014 at 07:15:04PM +0200, Ville Syrjälä wrote:
> > > As a side note if someone is looking for stuff to do, then the pin/unpin
> > > logic might be good
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=247/348->276/348
PNV: pass/total=326/328->327
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=247/348->277/348
PNV: pass/total=326/328->324
The block was added for spin_lock_irqsave flags, but since the locking
was converted to spin_lock_irq variant, the block is no longer needed.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/
On 12/11/2014 11:24, Chris Wilson wrote:
On Wed, Nov 12, 2014 at 10:53:26AM +, Nick Hoath wrote:
seq_putc(m, '\n');
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index afa9c35..0fe238c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers
On Tue, Nov 11, 2014 at 10:30:57AM +0100, Daniel Vetter wrote:
> On Mon, Nov 10, 2014 at 07:15:04PM +0200, Ville Syrjälä wrote:
> > As a side note if someone is looking for stuff to do, then the pin/unpin
> > logic might be good thing to look at. We're currently a bit inconsistent
> > whether we ha
On Wed, Nov 12, 2014 at 10:28:10AM +0100, Daniel Vetter wrote:
> On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> > > From: Mika Kuoppala
> > >
> > > As per latest pm guide, we need to do this also on
> > > past hsw
On Wed, Nov 12, 2014 at 10:53:26AM +, Nick Hoath wrote:
seq_putc(m, '\n');
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index afa9c35..0fe238c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2027,
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=247/348->276/348
PNV: pass/total=326/328->324
While looking through drm_crtc.c to double-check make locking changes
I've noticed that there's a few other places that would now benefit
from simplified return value handling.
So let's flatten the control flow and replace and always 0 ret with 0
where possible.
Signed-off-by: Daniel Vetter
---
Where there were duplicate variables for the tail, context and ring (engine)
in the gem request and the execlist queue item, use the one from the request
and remove the duplicate from the execlist queue item.
Issue: VIZ-4274
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
This patchset merges execlist queue items in to gem requests. It does this by
using the reference count added by John Harrison's "Replace seqno values with
request structures" patchset to ensure that the gem request is available for
the whole execlist submission lifespan.
v2: merge intel_ctx_sub
Move all remaining elements that were unique to execlists queue items
in to the associated request.
Signed-off-by: Nick Hoath
Issue: VIZ-4274
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++
drivers/gpu/drm/i915/i915_drv.h | 22 +
drivers/gpu/drm/i915/i915_gem.c | 6
Add a reference and pointer from the execlist queue item to the associated
gem request. For execlist requests that don't have a request, create one
as a placeholder.
This patchset requires John Harrison's "Replace seqno values with request
structures"
patchset.
Issue: VIZ-4274
Signed-off-by: Nic
Signed-off-by: Nick Hoath
Issue: VIZ-4274
---
drivers/gpu/drm/i915/intel_lrc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b6ec012..f3f1428 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/d
The first pass implementation of execlists required a backpointer to the
context to be held
in the intel_ringbuffer. However the context pointer is available higher in the
call stack.
Remove the backpointer from the ring buffer structure and instead pass it down
through the
call stack.
v2: Inte
The check tests require AM_TESTS_ENVIRONMENT, which was added in
automake 1.12.
Signed-off-by: Thomas Wood
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index a2569b8..bb0b16d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -35,7
TESTS_scripts was accidentally removed from EXTRA_DIST in commit 685e577
(Move library selftests to lib/tests).
Cc: Daniel Vetter
Signed-off-by: Thomas Wood
---
tests/Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 8893
On Fri, Nov 07, 2014 at 02:22:02PM -0800, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> This patch sets up all of the tracking and copying necessary to
> use batch pools with the command parser and dispatches the copied
> (shadow) batch to the hardware.
>
> After this patch, the pars
On Wed, Nov 12, 2014 at 09:44:34AM +0100, Daniel Vetter wrote:
> On Fri, Nov 07, 2014 at 02:22:01PM -0800, bradley.d.vol...@intel.com wrote:
> > + if (obj && obj->madv == __I915_MADV_PURGED) {
> > + was_purged = true;
> > + list_del(&obj->batch_pool_lis
On Tue, Nov 11, 2014 at 12:30:46PM -0800, Jesse Barnes wrote:
> This is useful for checking things later.
>
> v2:
> - fix hsw infoframe enabled check (Ander)
> v3:
> - set infoframe status in compute_config too (Ville)
>
> Signed-off-by: Jesse Barnes
Squashed into the original patch, thanks
On Fri, Nov 07, 2014 at 02:22:01PM -0800, bradley.d.vol...@intel.com wrote:
> +struct drm_i915_gem_object *
> +i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool,
> + size_t size)
> +{
> + struct drm_i915_gem_object *obj = NULL;
> + struct drm_i915_gem_object *tmp,
On Wed, Nov 12, 2014 at 09:52:20AM +0200, Jani Nikula wrote:
> On Tue, 11 Nov 2014, Ville Syrjälä wrote:
> > On Tue, Nov 11, 2014 at 04:48:03PM +0200, Jani Nikula wrote:
> >> Don't save the panel power sequencer register on vlv/chv for two simple
> >> reasons. First, these are the wrong registers
On Fri, Nov 07, 2014 at 02:22:07PM -0800, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> Move it to a separate function since the main do_execbuffer function
> already has so much going on.
>
> Signed-off-by: Brad Volkin
> ---
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 136
> ++
On Mon, Nov 10, 2014 at 02:56:50PM +, Robert Bragg wrote:
> This adds i915_gem_context_pin/unpin_state functions so that code
> outside i915_gem_context.c can pin/unpin a context without duplicating
> knowledge about the alignment constraints.
>
> Signed-off-by: Robert Bragg
At first I've th
On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> > From: Mika Kuoppala
> >
> > As per latest pm guide, we need to do this also on
> > past hsw.
>
> Yep, matches the doc.
>
> Reviewed-by: Ville Syrjälä
Queued for -
On Tue, Nov 11, 2014 at 10:34:15AM -0800, Jesse Barnes wrote:
> On Tue, 11 Nov 2014 09:29:18 -0800
> Bob Paauwe wrote:
>
> > Use the new pipe config values to calculate the updated pll dividers.
> >
> > This regression was introduced in
> >
> > commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
>
On Fri, Nov 07, 2014 at 03:55:18PM -0800, Rodrigo Vivi wrote:
> Let's document PSR a bit. No functional changes.
>
> Signed-off-by: Rodrigo Vivi
I've tried to merge the preceeding patches to avoid rebase pain, but
there's conflicts. I think it'd be best if we get those patches into shape
first.
On Fri, Nov 07, 2014 at 03:55:15PM -0800, Rodrigo Vivi wrote:
> Let's use VBT + 1 now we parse it.
This patch completely lacks the justification for why we need this. Please
add a short summary of our previous discussion with Art.
>
> v2: fix subject and consider that idle_frame = 2 is another f
On Fri, Nov 07, 2014 at 02:22:00PM -0800, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> This is v4 of the series I sent here:
> http://lists.freedesktop.org/archives/intel-gfx/2014-November/054733.html
>
> This version incorporates most of the feedback from v3. The couple of things
>
On Fri, Nov 07, 2014 at 02:22:06PM -0800, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> By adding a new exec_entry flag, we cleanly mark the shadow objects
> as purgeable after they are on the active list.
>
> Signed-off-by: Brad Volkin
> ---
> drivers/gpu/drm/i915/i915_gem_execbuf
On Fri, Nov 07, 2014 at 02:22:01PM -0800, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> This adds a small module for managing a pool of batch buffers.
> The only current use case is for the command parser, as described
> in the kerneldoc in the patch. The code is simple, but separatin
On Tue, Nov 11, 2014 at 04:12:22PM +, Chris Wilson wrote:
> On Tue, Nov 11, 2014 at 04:13:09PM +0100, Daniel Vetter wrote:
> > On Sat, Nov 08, 2014 at 08:25:04AM +, Chris Wilson wrote:
> > > On Fri, Nov 07, 2014 at 02:25:38PM -0800, O'Rourke, Tom wrote:
> > > > On Fri, Nov 07, 2014 at 10:41
On Tue, Nov 11, 2014 at 04:47:33PM +, Michel Thierry wrote:
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 98f2787..9e17432 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -6
On Tue, Nov 11, 2014 at 06:59:52PM +0200, Mika Kuoppala wrote:
> Michel Thierry writes:
>
> > Following the legacy ring submission example, update the
> > ring->init_context() hook to support the execlist submission mode.
> >
> > v2: update to use the new workaround macros and cleanup unused code
On Tue, Nov 11, 2014 at 06:10:50PM +0200, Mika Kuoppala wrote:
> Michel Thierry writes:
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index f0e7761..a6c4458 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/
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