[1.396361] [ cut here ]
[1.396396] WARNING: CPU: 2 PID: 108 at
/home/airlied/devel/kernel/drm-next/drivers/gpu/drm/i915/intel_display.c:997
intel_disable_pipe+0x2ae/0x2c0 [i915]()
[1.396397] pipe_off wait timed out
[1.396401] Modules linked in: i915 i2c_algo_
This is wrong.
A skl_enable_backlight must be created setting c8254 propperly without the
shift 16. Also maybe setting c8354h.
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> From: Satheeshakrishna M
>
> Extending the BDW backlight implementation to SKL.
>
> Signed-off-by: Satheeshakr
isn't fdi_link_training needed?
if not: Reviewed-by: Rodrigo Vivi
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> From: Satheeshakrishna M
>
> Set gen 9 function pointers for eld write and global resource.
> Implementation remains same as HSW.
>
> v2: Rebase on top of Sonika's untangl
Again, PIPE_MISC has differences, but this dither set part is identical!
So:
Reviewed-by: Rodrigo Vivi
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> From: Satheeshakrishna M
>
> Pipe misc programming in gen9 is similar to BDW. Extending the BDW
> implementation to gen 9.
>
> Signed-
the rest of DE_PIPE_INTERRUPT definition is different from BDW to SKL but
the underrun is indeed the same!
Reviewed-by: Rodrigo Vivi
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> 1 file changed, 1 inser
I just noticed this is a "legacy" mode 48b and standard for skl would be a
64b aligned..
But anyway this seems to be the right for now so
Reviewed-by: Rodrigo Vivi
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_gpu_erro
Reviewed-by: Rodrigo Vivi
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.
This seems to allow more than just the RCS timestamp, but also allow
the I915_REG_READ ioctl for gen9.
Anyway:
Reviewed-by: Rodrigo Vivi
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 1 file changed,
This already has the ideal rv-b ;)
But feel free to also use:
Reviewed-by: Rodrigo Vivi
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> gen9 uses very similar memory management to what gen8 has. Just follow
> the flow.
>
> v2: Fix trivial conflict (Damien)
>
> Reviewed-by: Ben Widawsky
Reviewed-by: Rodrigo Vivi
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> Skylake doesn't use the pre-charge field now, but, instead, we need to
> specify the total number of SYNC pulses for the SYNC phase (pre-charge +
> SYNC pattern pules). Let's use the default value (32) for that.
>
I believe this patch should remove the gen9 part of
ilk_get_aux_clock_divider.
Also there it just returns 0, but here it returns 0 or 1 depending on the
index.
This also is incoherent with the commit description.
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> We need to provide a vfunc
On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau
wrote:
> Skylake makes primary planes the same as sprite planes and call the
> result "universal planes".
>
> This commit emulates a primary plane with plane 0, taking the
> opportunity to redefine primary and sprite registers to be identical now
> t
The panel has to be reconfigured only when it really loose the power.
The traditional enable/disable sequence already take care of this so we can
minimize the time spend on every re-enable.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 8
1 file changed, 4 insertions
We don't need to setup everything else if it doesn't match all conditions.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 271788
Let's make sure PSR is propperly disabled before to re-enabled it.
According to Spec, after disabled PSR CTL, the Idle state might occur
up to 24ms, that is one full frame time (1/refresh rate),
plus SRD exit training time (max of 6ms),
plus SRD aux channel handshake (max of 1.5ms).
So if somethi
psr_enabled is already by itself a setup once so let's put the W/As there and
rename old setup once to setup_vsc.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/
In some cases like when PSR just got enabled the panel need more vblank
times to calculate CRC. I figured that out with the new PSR test cases
facing some cases that I had a green screen but a blank CRC. Even with
2 vblank waits on kernel + 2 vblank waits on test case.
So let's give up to 6 vblank
Also enable the ring->init_context() hook for chv in execlist submission
mode.
For: VIZ-4092
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c| 37 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 37 -
drivers/g
Following the legacy ring submission example, update the
ring->init_context() hook to support the execlist submission mode.
Workarounds are defined in bdw_emit_workarounds(), but the emit
now depends on the ring submission mode.
For: VIZ-4092
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i9
On Tue, Sep 16, 2014 at 04:19:07PM +0300, Imre Deak wrote:
> On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 93bd9bf..a983b40 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers
Hi, the same happens with 3.17-rc5. The kernel is unfortunately
unusable with my external monitor because after some plug, unplug
and suspend to RAM cycles the behaviour is not good (sometimes
it freezes, sometimes X needs a restart).
Sorry to ask, but is there someone looking at this? I can prov
On 4 September 2014 12:26, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
Does the X tiling alignment value need to be set too?
A minor point, but perhaps use KB in the subject rather than Kb?
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1
On 4 September 2014 12:26, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
While discussing this with Damien, he mentioned that legacy ring
buffer submission is not supported on gen 9 and perhaps
dispatch_execbuffer should be set to null instead.
> ---
> drivers/gpu/drm/i915/intel_ringb
On 4 September 2014 15:16, Damien Lespiau wrote:
> Of course, the series now needs reviewers. There's a list of known
> problems that I'm planning to address, a few of those problems are easy
> to solve and ca be addressed as a new revision of those pathes. However
> I'm hoping other ones can be f
On Tue, 2014-09-16 at 16:56 +0300, Imre Deak wrote:
> On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote:
> > From: Satheeshakrishna M
> >
> > This patch implements core logic of SKL display power well.
> >
> > FIXME: hsw_pwr needs to go. The audio guys promised us that they'll do a
> > pr
On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote:
> From: Satheeshakrishna M
>
> Earlier it was thought that MISC IO is always ON power well.
> But it doesn't looks like the case as confirmed by the HW team.
> Adding code to enable/disable MISC IO power well.
>
> v2: Use power well data f
On Wed, Sep 10, 2014 at 09:04:04PM +0300, Ville Syrjälä wrote:
> > +#define PLANE_WM_TRANS_1(pipe) \
> > + _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
> > +#define PLANE_WM_TRANS_2(pipe) \
> > + _PIPE(pipe, PLANE_WM_TRANS_2_A_0
On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote:
> From: Satheeshakrishna M
>
> This patch implements core logic of SKL display power well.
>
> FIXME: hsw_pwr needs to go. The audio guys promised us that they'll do a
> proper
> implementation for skl+.
>
> v2: Addressed Imre's comments
From: Zhe Wang
Implement common forcewake functions shared by Gen9 features.
v2: Make the focewake_{get,put} functions static (Mika)
Small coding style fix in the function definition (Damien)
Reviewed-by: Mika Kuoppala
Signed-off-by: Zhe Wang (v1)
Signed-off-by: Damien Lespiau (v2)
---
On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote:
> From: Satheeshakrishna M
>
> This patch enables power well 2 required for any aux transaction.
>
> v2: Implemented Imre's comments
> - In EDID/DPCD related routines, request AUX power well in SKL
>
> v3: Implemented Imre's comment
On Thu, Sep 04, 2014 at 03:21:16PM +0200, Daniel Vetter wrote:
> On Thu, Sep 04, 2014 at 12:27:04PM +0100, Damien Lespiau wrote:
> > SKL Uses the same hardware for all planes now, so called "universal"
> > planes. Ie both the primary planes and sprite planes share the same
> > logic. This patch imp
On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote:
> From: Satheeshakrishna M
>
> Defining new bit fields for SKL display power wells.
>
> v2: Clean up unused macros
>
> Signed-off-by: Satheeshakrishna M
> Signed-off-by: Damien Lespiau
This looks ok, but it should be squashed into 71/8
On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote:
> From: Satheeshakrishna M
>
> Adding new power doamins for AUX controllers
>
> v2: Added new power domains in power_domain_str per Imre's comment
>
> v3: Added AUX power domains to older platforms
>
> v4: Rebase on top of POWER_DOMAIN_P
On Mon, Sep 15, 2014 at 07:21:50PM -0400, Rodrigo Vivi wrote:
> In some cases like when PSR just got enabled the panel need more vblank
> times to calculate CRC. I figured that out with the new PSR test cases
> facing some cases that I had a green screen but a blank CRC. Even with
> 2 vblank waits
On Mon, Sep 15, 2014 at 07:24:03PM -0400, Rodrigo Vivi wrote:
> If something while getting panel CRC this means that probably hw I/O error
> so hw is busted and try again shouldn't help much.
>
> Signed-off-by: Rodrigo Vivi
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/dr
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