One small change I forgot to make in
commit c4d69da167fa967749aeb70bc0e94a457e5d00c1
Author: Chris Wilson
Date: Mon Sep 8 14:25:41 2014 +0100
drm/i915: Evict CS TLBs between batches
was to update the copy width for the compact BLT copy instruction.
Reported-by: Thomas Richter
Signed-off
From: gsarora
Extended intel_sprite_on functionality to display all the
available sprite planes on a particular connector.
Signed-off-by: Gagandeep S Arora
---
demos/intel_sprite_on.c | 138 ++--
1 file changed, 87 insertions(+), 51 deletions(-)
dif
From: Gustavo Padovan
7e4bf45dbd99a965c7b5d5944c6dc4246f171eb5 introduced the regression.
We fix it by doing the right assignment of crtc_y
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83747
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
1 file changed
On Thu, Sep 11, 2014 at 09:30:27AM -0700, Volkin, Bradley D wrote:
> On Thu, Sep 11, 2014 at 01:49:07AM -0700, Chris Wilson wrote:
> > vma->exec_entry = memset(&dummy_exec_entry, 0, sizeof(dummy_exec_entry);
> >
> > Then you can kill the additional if (entry) checks.
>
> Also, don't we need to se
From: gsarora
Extended intel_sprite_on functionality to display all the
available sprite planes on a particular connector.
Signed-off-by: Gagandeep S Arora
---
demos/intel_sprite_on.c | 138 ++--
1 file changed, 87 insertions(+), 51 deletions(-)
dif
Chris Wilson writes:
> That extra alignment is due to gen2 and early gen3 (if
> (!intel->has_relaxed_fencing) covers them).
Here's the patch which changed the alignment requirment:
commit 736b89504a32239a0c7dfb5961c1b8292dd744bd
Author: Chris Wilson
Date: Sun Dec 30 1
On Thu, 04 Sep 2014 10:53:44 +0300
Jani Nikula wrote:
> On Tue, 02 Sep 2014, Jani Nikula wrote:
> > On Tue, 02 Sep 2014, Jani Nikula wrote:
> >> How about throwing this at any eDP link parameter bugs and
> >> regressions? Does it feel too much like giving up the battle?
> >
> > Fixes at least o
On Tue, 26 Aug 2014 13:09:54 -0400
Charles Devereaux wrote:
> Hello
>
> I'm trying to use i915.fastboot on a Thinkpad X60t. The bios has been
> replaced by coreboot, which supports native video init.
>
> The goal is to boot to a console on a debian in less than 2 seconds
> (kernel
> + systemd),
On Tue, 2 Sep 2014 13:45:37 +0300
Ville Syrjälä wrote:
> On Tue, Sep 02, 2014 at 09:24:48AM +0100, Chris Wilson wrote:
> > As we may query the edid multiple times following a detect, record
> > the EDID found during output discovery and reuse it. This is a
> > separate issue from caching the outp
On Fri, 05 Sep 2014, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Due to the upcoming atomic modesetting feature we need to separate
> some update functions into a check step that can fail and a commit
> step that should, ideally, never fail.
>
> This commit splits intel_update_plane() and
On Thu, Sep 11, 2014 at 01:49:07AM -0700, Chris Wilson wrote:
> On Thu, Sep 11, 2014 at 11:39:46AM +0300, Mika Kuoppala wrote:
> > When PPGGT is in use, we need to bind secure batches also to ggtt.
> > We used to pin, exec and unpin. This trick worked as there was nothing
> > competing in ggtt spac
On Thu, Sep 11, 2014 at 09:08:12AM +0100, Chris Wilson wrote:
> On Thu, Sep 11, 2014 at 10:02:27AM +0200, Daniel Vetter wrote:
> > On Wed, Sep 10, 2014 at 07:52:19PM +0100, Chris Wilson wrote:
> > > If we believe that the device can cross cache domains in its prefetcher
> > > (i.e. we allow neighbo
From: Gustavo Padovan
Fold intel_pipe_set_base() in the update primary plane path merging
pieces of code that are common to both paths.
Basically the the pin/unpin procedures are the same for both paths
and some checks can also be shared (some of the were moved to the
check() stage)
v2: take Vi
On Thu, 11 Sep 2014 14:59:35 +0300
Imre Deak wrote:
> On Thu, 2014-09-11 at 08:49 +0100, Chris Wilson wrote:
> > On Wed, Sep 10, 2014 at 06:17:01PM +0300, Imre Deak wrote:
> > > Since correctness wins over optimal code and since the optimization
> >
> > Optimal code is also correct ;-) s/optimal
On Thu, 2014-09-11 at 11:02 +0200, Daniel Vetter wrote:
> On Wed, Sep 10, 2014 at 09:38:50PM +0300, Imre Deak wrote:
> > On Wed, 2014-09-10 at 17:52 +0200, Daniel Vetter wrote:
> > > On Wed, Sep 10, 2014 at 06:16:53PM +0300, Imre Deak wrote:
> > > > The first part of the patchset (1-6) fixes an S4
On Thu, 2014-09-11 at 11:00 +0200, Daniel Vetter wrote:
> On Wed, Sep 10, 2014 at 06:16:57PM +0300, Imre Deak wrote:
> > i915_suspend() is called from the DRM legacy S3 suspend/S4 freeze paths
> > and the switcheroo suspend path. For switcheroo we only ever need to
> > perform a full suspend (PM_EV
On Thu, Sep 11, 2014 at 12:51:37PM +0100, John Harrison wrote:
>Will the PPGTT fix be sent out soon? If not, can you just send me a quick
>fix directly?
I was hoping to gather some feedback before the next send. Patch
incorporated into
http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?
On Thu, 2014-09-11 at 08:49 +0100, Chris Wilson wrote:
> On Wed, Sep 10, 2014 at 06:17:01PM +0300, Imre Deak wrote:
> > Since correctness wins over optimal code and since the optimization
>
> Optimal code is also correct ;-) s/optimal/just plain broken/
Yes, bad wording. To clarify, since the opt
On Thu, 2014-09-11 at 08:47 +0100, Chris Wilson wrote:
> On Wed, Sep 10, 2014 at 06:17:02PM +0300, Imre Deak wrote:
> > Checking for GT faults is not specific in any way to S4 thaw, so do it
> > also during S3 resume and S4 restore. This allows us to unify the
> > handlers for these events in an up
Will the PPGTT fix be sent out soon? If not, can you just send me a
quick fix directly?
Also, noticed that in 'submit_execbuf()', if the 'copy_from_user()' call
fails then it jumps to the error return but does not set 'ret' thus will
actually return success. Also, there seems to be a mix of 'g
Based upon a patch from Deepak, but reworked to only apply on gen7+
and with the logic a bit clarified.
Cc: Deepak S
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 13 +++--
drivers/gpu/drm/i915/i915_reg.h| 8
2 files changed, 19 insertions(+
On Thu, Sep 11, 2014 at 01:54:44PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
> exceeds 95% of the core display clock. Apparently this can cause
> underruns.
>
> There's no similar restriction listed fo
Hi Mario,
Can you please take a look at the patches I've submitted and review
them (at least the first 2)? Dave will close the 3.18 drm-next merge
window at the end of this week and I'd like to really get this in.
Thanks, Daniel
On Wed, Sep 10, 2014 at 5:45 PM, Mario Kleiner
wrote:
> On Wed, S
From: Ville Syrjälä
Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
exceeds 95% of the core display clock. Apparently this can cause
underruns.
There's no similar restriction listed for HSW, so leave that one alone
for now.
Tested-by: Timo Aaltonen
Bugzilla: https://bugs.fre
On Thu, Sep 11, 2014 at 10:49:01AM +0200, Daniel Vetter wrote:
> On Thu, Sep 11, 2014 at 10:18 AM, Sharma, Shashank
> wrote:
> > Thanks Bob, Matt, Daniel for the review.
> > I will create a new patch set, complying all (almost :)) review comments
> > from you all, and will float for review.
> >
>
On Wed, Sep 10, 2014 at 09:38:50PM +0300, Imre Deak wrote:
> On Wed, 2014-09-10 at 17:52 +0200, Daniel Vetter wrote:
> > On Wed, Sep 10, 2014 at 06:16:53PM +0300, Imre Deak wrote:
> > > The first part of the patchset (1-6) fixes an S4 bug on VLV introduced
> > > recently. The rest unifies the vario
On Wed, Sep 10, 2014 at 06:16:57PM +0300, Imre Deak wrote:
> i915_suspend() is called from the DRM legacy S3 suspend/S4 freeze paths
> and the switcheroo suspend path. For switcheroo we only ever need to
> perform a full suspend (PM_EVENT_SUSPEND) and for the DRM legacy path
> we can handle the S4
On Wed, Sep 10, 2014 at 06:17:01PM +0300, Imre Deak wrote:
> The logic to skip restoring GTT mappings was added to speed up
> suspend/resume, but not on old GENs where not restoring them caused
> problems. The check for old GENs is based on the existance of OpRegion,
> but this doesn't work since o
On Thu, Sep 11, 2014 at 10:18 AM, Sharma, Shashank
wrote:
> Thanks Bob, Matt, Daniel for the review.
> I will create a new patch set, complying all (almost :)) review comments from
> you all, and will float for review.
>
> Points I noted down overall:
> 1. No need for separate arrays for names,
On Thu, Sep 11, 2014 at 11:39:46AM +0300, Mika Kuoppala wrote:
> When PPGGT is in use, we need to bind secure batches also to ggtt.
> We used to pin, exec and unpin. This trick worked as there was nothing
> competing in ggtt space and the ppggt vma was used to tracking.
> But this left the ggtt vma
When PPGGT is in use, we need to bind secure batches also to ggtt.
We used to pin, exec and unpin. This trick worked as there was nothing
competing in ggtt space and the ppggt vma was used to tracking.
But this left the ggtt vma untracked and potentially it could vanish
during the batch execution.
Thanks Bob, Matt, Daniel for the review.
I will create a new patch set, complying all (almost :)) review comments from
you all, and will float for review.
Points I noted down overall:
1. No need for separate arrays for names, sizes etc (:( )
2. Create a _set_blob for blob_properties, and tak
On Thu, Sep 11, 2014 at 10:02:27AM +0200, Daniel Vetter wrote:
> On Wed, Sep 10, 2014 at 07:52:19PM +0100, Chris Wilson wrote:
> > If we believe that the device can cross cache domains in its prefetcher
> > (i.e. we allow neighbouring pages in different domains), we don't supply
> > a color_adjust
On Wed, Sep 10, 2014 at 07:52:19PM +0100, Chris Wilson wrote:
> If we believe that the device can cross cache domains in its prefetcher
> (i.e. we allow neighbouring pages in different domains), we don't supply
> a color_adjust callback. Use the presence of this callback to better
> determine when
On Wed, Sep 10, 2014 at 11:15:11AM -0700, Matt Roper wrote:
> On Wed, Sep 10, 2014 at 04:38:43PM +0530, Sharma, Shashank wrote:
> > Hello Matt,
> >
> > Thanks for your detailed descriptions, reviews comments and time.
> > Please find my comments inline.
> >
> > Regards
> > Shashank
> > On 9/10/20
On Wed, Sep 10, 2014 at 03:17:34PM -0700, Matt Roper wrote:
> On Tue, Sep 09, 2014 at 11:53:15AM +0530, shashank.sha...@intel.com wrote:
> > From: Shashank Sharma
> >
> > This patch adds support for CSC correction color property.
> > It does the following:
> > 1. Creates a new DRM property for CS
On Wed, Sep 10, 2014 at 02:17:02PM -0700, Matt Roper wrote:
> On Wed, Sep 10, 2014 at 04:50:56PM +0530, Sharma, Shashank wrote:
> ...
> > >>+
> > >>+/* Properties */
> > >>+enum clrmgr_tweaks {
> > >>+ csc = 0,
> > >>+ gamma,
> > >>+ contrast,
> > >>+ brightness,
> > >>+ hue_saturation,
> > >>+ clr
On Wed, Sep 10, 2014 at 06:17:01PM +0300, Imre Deak wrote:
> Since correctness wins over optimal code and since the optimization
Optimal code is also correct ;-) s/optimal/just plain broken/
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
__
On Wed, Sep 10, 2014 at 06:17:02PM +0300, Imre Deak wrote:
> Checking for GT faults is not specific in any way to S4 thaw, so do it
> also during S3 resume and S4 restore. This allows us to unify the
> handlers for these events in an upcoming patch.
So why not just move i915_check_and_clear_faults
If we believe that the device can cross cache domains in its prefetcher
(i.e. we allow neighbouring pages in different domains), we don't supply
a color_adjust callback. Use the presence of this callback to better
determine when we should be verifying that the GTT space we just
used is valid.
v2:
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