On Mon, May 12, 2014 at 10:02 AM, Yang, Rong R wrote:
> Hi, Ken,
>
> Thanks for your patch.
> But how do you release your driver on the HSW products? If can't LRI/LRM
> from userspace batches, almost all of OpenCL application can't run.
> So if I want to announce that the OpenCL drive
On Tue, May 13, 2014 at 12:37 AM, Jesse Barnes wrote:
> Like on ILK, the pipe won't be running until later on.
Like on ilk?! Since when is vlv display derived from that? "[PATCH
3/4] drm/i915: Kill vblank waits after pipe enable on gmch platforms"
from Ville makes a more consistent impression to
Daniel,
Please find my comments inline.
Regards
Shashank
On 5/12/2014 8:58 PM, Daniel Vetter wrote:
On Mon, May 12, 2014 at 05:35:13PM +0530, Sharma, Shashank wrote:
Thanks for your time and the comments David.
please find mine inline.
Regards
Shashank
On 5/12/2014 5:20 PM, David Herrmann wrot
On Mon, 2014-05-12 at 13:04 -0600, Daniel Vetter wrote:
> On Fri, May 09, 2014 at 01:44:59PM +0100, oscar.ma...@intel.com wrote:
> > From: Oscar Mateo
> >
> > This is missing in:
> >
> > commit 78325f2d270897c9ee0887125b7abb963eb8efea
> > Author: Ben Widawsky
> > Date: Tue Apr 29 14:52:29 201
Like on ILK, the pipe won't be running until later on.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c65e7f7..c66d2ea 100644
--- a/drive
On Mon, May 12, 2014 at 11:35:20AM +0100, Thomas Wood wrote:
> Add a function to stop and fail a test after the specified number of
> seconds have elapsed.
>
> Signed-off-by: Thomas Wood
> ---
> lib/igt_core.c | 44 +---
> lib/igt_core.h | 2 ++
> 2 files
On Thu, May 08, 2014 at 07:23:13PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Use the same code for enabling/disabling planes on all platforms. Rename
> the functions to reflect that they're no longer specific to any
> platform.
>
> For now we leave the plane enable/di
On Mon, May 12, 2014 at 01:30:39PM -0600, Alex Williamson wrote:
> On Mon, 2014-05-12 at 21:08 +0200, Daniel Vetter wrote:
> > On Fri, May 09, 2014 at 02:20:41PM -0600, Alex Williamson wrote:
> > > Commit 81b5c7bc found that the current VGA arbiter support in i915
> > > only works for ancient GMCH-
On Mon, 2014-05-12 at 21:08 +0200, Daniel Vetter wrote:
> On Fri, May 09, 2014 at 02:20:41PM -0600, Alex Williamson wrote:
> > Commit 81b5c7bc found that the current VGA arbiter support in i915
> > only works for ancient GMCH-based IGD devices and attempted to update
> > support for newer HD device
On Fri, May 09, 2014 at 02:20:41PM -0600, Alex Williamson wrote:
> Commit 81b5c7bc found that the current VGA arbiter support in i915
> only works for ancient GMCH-based IGD devices and attempted to update
> support for newer HD devices. Unfortunately newer devices cannot
> completely opt-out of V
On Fri, May 09, 2014 at 01:44:59PM +0100, oscar.ma...@intel.com wrote:
> From: Oscar Mateo
>
> This is missing in:
>
> commit 78325f2d270897c9ee0887125b7abb963eb8efea
> Author: Ben Widawsky
> Date: Tue Apr 29 14:52:29 2014 -0700
>
> drm/i915: Virtualize the ringbuffer signal func
>
> Lo
On Mon, May 12, 2014 at 01:25:24PM +0200, Jörg Otte wrote:
> 2014-05-11 18:49 GMT+02:00 Daniel Vetter :
> > On Sat, May 10, 2014 at 10:52 AM, Jörg Otte wrote:
> >>> On Fri, May 09, 2014 at 05:14:38PM +0100, Damien Lespiau wrote:
> On Fri, May 09, 2014 at 06:11:37PM +0200, Jörg Otte wrote:
> >
On Mon, May 12, 2014 at 08:46:24PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The kernel full ppgtt support has a bug where it can drop a pinned
> fence to the floor, hence we leak the pin_count as the subsequent
> fence unpin becomes a nop. We can trigger it easily by
On 05/12/2014 08:54 AM, Daniel Vetter wrote:
> On Mon, May 12, 2014 at 08:23:45AM -0700, Randy Dunlap wrote:
>> On 05/12/2014 01:58 AM, Daniel Vetter wrote:
>>> On Mon, May 12, 2014 at 06:24:57PM +1000, Dave Airlie wrote:
>>
>> If we decide to go for property documentation inside the source
On 05/12/2014 01:02 AM, Yang, Rong R wrote:
> Hi, Ken,
>
> Thanks for your patch. But how do you release your driver on the HSW
> products? If can't LRI/LRM from userspace batches, almost all of
> OpenCL application can't run. So if I want to announce that the
> OpenCL driver support HSW, it must
On Mon, May 12, 2014 at 01:27:25PM +0300, Ville Syrjälä wrote:
> On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
> > Adding relevant read out comparison code, in check_crtc_state, for the new
> > member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
> > values for
On Mon, May 12, 2014 at 06:35:04PM +0300, Imre Deak wrote:
> In
>
> commit c6df39b5ea6342323a42edfbeeca0a28c643d7ae
> Author: Imre Deak
> Date: Mon Apr 14 20:24:29 2014 +0300
>
> drm/i915: get a runtime PM ref for the deferred GT powersave enabling
>
> I added an RPM get-ref when enabling
From: Ville Syrjälä
The kernel full ppgtt support has a bug where it can drop a pinned
fence to the floor, hence we leak the pin_count as the subsequent
fence unpin becomes a nop. We can trigger it easily by unbinding a
buffer from a ppgtt address space while the buffer is simultaneosly
being use
On Mon, May 12, 2014 at 09:41:02AM -0700, Volkin, Bradley D wrote:
> On Mon, May 12, 2014 at 09:24:06AM -0700, Daniel Vetter wrote:
> > On Thu, May 08, 2014 at 09:02:18AM -0700, Volkin, Bradley D wrote:
> > > On Thu, May 08, 2014 at 08:45:07AM -0700, Ville Syrjälä wrote:
> > > > On Thu, May 08, 201
On Thu, May 08, 2014 at 10:19:42PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> gen8_stolen_size() is missing __init, so add it.
>
> Also all the intel_stolen_funcs structures can be marked
> __initconst.
>
> intel_stolen_ids[] can also be made const if we replace the
>
On Wed, Apr 30, 2014 at 04:11:27PM +0300, Imre Deak wrote:
> On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Add chv_crtc_clock_get() to read out the DPLL settings.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/int
On Mon, 12 May 2014, Daniel Vetter wrote:
> Inspired by a review bikeshed from Jani.
>
Reviewed-by: Jani Nikula
> Cc: Jani Nikula
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_irq.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/driv
On Thu, Apr 10, 2014 at 08:56:46PM +0300, Jani Nikula wrote:
> On Wed, 09 Apr 2014, Daniel Vetter wrote:
> > On Wed, Apr 09, 2014 at 01:28:23PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> >> From: Ville Syrjälä
> >>
> >> No CRT output on CHV, so don't call intel_crt_init().
> >>
> >> v2:
On Wed, Apr 30, 2014 at 03:13:53PM +0300, Imre Deak wrote:
> On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Chon Ming Lee
> >
> > Added programming phy layer for CHV based on "Application note for 1273
> > CHV Display phy".
> >
> > v2: Rebase the code and do so
On Mon, Apr 28, 2014 at 05:54:24PM +0300, Imre Deak wrote:
> On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Chon Ming Lee
> >
> > During cold boot, the display controller needs to deassert the common
> > lane reset. Only do it once during intel_init_dpio for bo
On Thu, May 08, 2014 at 06:10:45PM +0300, Jani Nikula wrote:
> On Thu, 08 May 2014, Ville Syrjälä wrote:
> > On Thu, May 08, 2014 at 05:32:21PM +0300, Jani Nikula wrote:
> >> On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> >> > From: Daniel Vetter
> >> >
> >> > Same as on other gen8 d
Inspired by a review bikeshed from Jani.
Cc: Jani Nikula
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_irq.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e5ec3e5ca37c..b10fbd
> I call this "review by asking for an igt" ;-) -Daniel
Ok, I´ll give it a try. At least I will learn something about the kms code,
a.k.a. "learning by igt" :D
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailm
From: Oscar Mateo
Or with a spinlock grabbed, because it might sleep, which is not
a nice thing to do. Instead, do the runtime_pm get/put together
with the create/destroy request, and handle the forcewake get/put
directly.
This can be squashed with:
[PATCH 35/50] drm/i915/bdw: Add forcewake loc
From: Ben Widawsky
For the most part, logical ring context objects are similar to hardware
contexts in that the backing object is meant to be opaque. There are
some exceptions where we need to poke certain offsets of the object for
initialization, updating the tail pointer or updating the PDPs.
arun.siluv...@linux.intel.com writes:
> From: "Siluvery, Arun"
>
> This patch adds support to have gem objects of variable size.
> The size of the gem object obj->size is always constant and this fact
> is tightly coupled in the driver; this implementation allows to vary
> its effective size usin
On Mon, May 12, 2014 at 01:39:00PM +0100, tim.g...@intel.com wrote:
> From: Tim Gore
>
> Until now the tests that depended on libcairo were simply
> skipped in the android build. Now that I have a cairo port
> working, build these cairo dependent tests if ANDROID_HAS_CAIRO
> is set to 1 in the en
On Mon, May 12, 2014 at 10:09:54AM +0300, Jani Nikula wrote:
> On Sun, 11 May 2014, Daniel Vetter wrote:
> > On Sun, May 11, 2014 at 11:02 AM, Dave Airlie wrote:
> >> On 11 May 2014 18:28, Thomas Meyer wrote:
> >>> Hi,
> >>>
> >>> 3.14.3 works as expected.
> >>> 3.15-rc5 shows a strange behaviou
On Mon, May 12, 2014 at 07:33:55AM +0100, Chris Wilson wrote:
> On Sun, May 11, 2014 at 07:40:57PM +0200, Daniel Vetter wrote:
> > On Sun, May 11, 2014 at 11:02 AM, Dave Airlie wrote:
> > > On 11 May 2014 18:28, Thomas Meyer wrote:
> > >> Hi,
> > >>
> > >> 3.14.3 works as expected.
> > >> 3.15-rc
On Sat, May 10, 2014 at 02:11:53PM -0700, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> The command parser in newer kernels will reject it and setting this
> bit is not required for the actual test case.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76670
> Signed-off-by
On Mon, May 12, 2014 at 03:49:02PM +0100, Tvrtko Ursulin wrote:
>
> On 05/10/2014 10:10 PM, bradley.d.vol...@intel.com wrote:
> >From: Brad Volkin
> >
> >For clients that submit large batch buffers the command parser has
> >a substantial impact on performance. On my HSW ULT system performance
> >
On Fri, May 09, 2014 at 07:02:08AM +0100, Chris Wilson wrote:
> On Thu, May 08, 2014 at 07:23:13PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Use the same code for enabling/disabling planes on all platforms. Rename
> > the functions to reflect that they're no long
On Fri, May 09, 2014 at 06:53:24AM +0100, Chris Wilson wrote:
> On Thu, May 08, 2014 at 07:23:16PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > We always enable vblank interrupts after the planes so move the call
> > into intel_crtc_enable_planes(). Later we will re
On Thu, May 08, 2014 at 02:33:47PM +, Lin, Mengdong wrote:
> Hi ,
>
> Are there any recent i915 patches that could possibly affect HDMI audio,
> during last two weeks?
>
> We got an audio regression on BDW that HDMI audio output becomes
> intermittent. Maybe HSW also has the same issue.
> I
On Thu, May 08, 2014 at 09:25:42AM +0300, Jani Nikula wrote:
> On Thu, 08 May 2014, Ben Widawsky wrote:
> > On Wed, May 07, 2014 at 09:42:57AM +0200, Daniel Vetter wrote:
> >> Aside: Please add the regression tags when handling bugs, I need those for
> >> tracking and stats.
> >> -Daniel
> >>
> >
On Mon, May 12, 2014 at 09:24:06AM -0700, Daniel Vetter wrote:
> On Thu, May 08, 2014 at 09:02:18AM -0700, Volkin, Bradley D wrote:
> > On Thu, May 08, 2014 at 08:45:07AM -0700, Ville Syrjälä wrote:
> > > On Thu, May 08, 2014 at 08:27:16AM -0700, Volkin, Bradley D wrote:
> > > > On Thu, May 08, 201
On Thu, May 08, 2014 at 01:18:40PM +0300, Ville Syrjälä wrote:
> On Thu, May 08, 2014 at 12:54:47PM +0300, Ville Syrjälä wrote:
> > On Wed, May 07, 2014 at 11:59:23PM +0300, Abdiel Janulgue wrote:
> > > On Wednesday, May 07, 2014 02:49:31 PM Ville Syrjälä wrote:
> > > > I quickly cobbled together a
On Sat, May 10, 2014 at 06:42:32AM -0700, Siluvery, Arun wrote:
> On 09/05/2014 22:18, Volkin, Bradley D wrote:
> > On Mon, Apr 28, 2014 at 08:01:29AM -0700, arun.siluv...@linux.intel.com
> > wrote:
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if (!i915_gem_obj_bound(obj, vm)) {
> >
On Thu, May 08, 2014 at 09:02:18AM -0700, Volkin, Bradley D wrote:
> On Thu, May 08, 2014 at 08:45:07AM -0700, Ville Syrjälä wrote:
> > On Thu, May 08, 2014 at 08:27:16AM -0700, Volkin, Bradley D wrote:
> > > On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
> > > >
> > > > Hi Brad,
On Fri, May 09, 2014 at 02:18:54PM -0700, Volkin, Bradley D wrote:
> On Mon, Apr 28, 2014 at 08:01:29AM -0700, arun.siluv...@linux.intel.com wrote:
> > From: "Siluvery, Arun"
> >
> > This patch adds support to have gem objects of variable size.
> > The size of the gem object obj->size is always c
On Mon, May 12, 2014 at 06:11:18PM +0200, Daniel Vetter wrote:
> On Mon, May 12, 2014 at 09:05:45AM +, Mateo Lozano, Oscar wrote:
> > Hi Daniel,
> >
> > Sorry, this fell through the cracks:
> >
> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Gracefully handle obj not
> > > bound to
> > > GG
On Mon, May 12, 2014 at 09:05:45AM +, Mateo Lozano, Oscar wrote:
> Hi Daniel,
>
> Sorry, this fell through the cracks:
>
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Gracefully handle obj not bound
> > to
> > GGTT in is_pin_display
> >
> > On Wed, Apr 02, 2014 at 07:21:01PM +0100, oscar.m
Hi
On Mon, May 12, 2014 at 5:28 PM, Daniel Vetter wrote:
> Those are all just reasons for atomic modeset and maybe an atomic modeget
> ioctl which transfers the entire blob of things. Maybe we should start
> with the atomic modeget to get things rolling. Otoh you can always do that
> in userspace
On Fri, May 09, 2014 at 06:30:11AM +0100, Chris Wilson wrote:
> On Thu, May 08, 2014 at 05:10:24PM -0700, Ben Widawsky wrote:
> > On Wed, Feb 26, 2014 at 04:41:41PM +, Tvrtko Ursulin wrote:
> > > +struct drm_i915_gem_userptr {
> > > + __u64 user_ptr;
> > > + __u64 user_size;
> > > + __u32 flags
On Mon, May 12, 2014 at 08:23:45AM -0700, Randy Dunlap wrote:
> On 05/12/2014 01:58 AM, Daniel Vetter wrote:
> > On Mon, May 12, 2014 at 06:24:57PM +1000, Dave Airlie wrote:
>
> If we decide to go for property documentation inside the source code
> then I
> believe we'll have t
In
commit c6df39b5ea6342323a42edfbeeca0a28c643d7ae
Author: Imre Deak
Date: Mon Apr 14 20:24:29 2014 +0300
drm/i915: get a runtime PM ref for the deferred GT powersave enabling
I added an RPM get-ref when enabling RPS from a deferred work, but forgot
to add the corresponding put-ref when c
Atm, we disable GT power saving during the end of the suspend sequence
in i915_save_state(). Doing the disabling at that point seems arbitrary.
One reason to disable it early though is to have a quiescent HW state
before we do anything else (for example save registers). So move the
disabling earlie
On Mon, May 12, 2014 at 05:35:13PM +0530, Sharma, Shashank wrote:
> Thanks for your time and the comments David.
> please find mine inline.
>
> Regards
> Shashank
> On 5/12/2014 5:20 PM, David Herrmann wrote:
> >Hi
> >
> >On Mon, May 12, 2014 at 12:26 PM, Sharma, Shashank
> > wrote:
> >>Benefits o
On 05/12/2014 01:58 AM, Daniel Vetter wrote:
> On Mon, May 12, 2014 at 06:24:57PM +1000, Dave Airlie wrote:
If we decide to go for property documentation inside the source code then I
believe we'll have to create our own format, as creating a properties table
from kerneldoc info
On 05/10/2014 10:10 PM, bradley.d.vol...@intel.com wrote:
From: Brad Volkin
For clients that submit large batch buffers the command parser has
a substantial impact on performance. On my HSW ULT system performance
drops as much as ~20% on some tests. Most of the time is spent in the
command loo
From: Deepak S
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
v2: Avoid vairable for freq request (ville)
Signed-off-by: Deepak S
Reviewed-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_irq.c | 12
1 file changed, 8 inser
On Sat, May 10, 2014 at 02:10:43PM -0700, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> For clients that submit large batch buffers the command parser has
> a substantial impact on performance. On my HSW ULT system performance
> drops as much as ~20% on some tests. Most of the time is
On Mon, May 12, 2014 at 11:35:20AM +0100, Thomas Wood wrote:
> Add a function to stop and fail a test after the specified number of
> seconds have elapsed.
>
> Signed-off-by: Thomas Wood
Looks like a useful helper to have in any case. Both patches are:
Acked-by: Damien Lespiau
--
Damien
> -
From: Tim Gore
Until now the tests that depended on libcairo were simply
skipped in the android build. Now that I have a cairo port
working, build these cairo dependent tests if ANDROID_HAS_CAIRO
is set to 1 in the environment.
For information on building cairo for IGT on Android see the
wiki at:
Thanks for your time and the comments David.
please find mine inline.
Regards
Shashank
On 5/12/2014 5:20 PM, David Herrmann wrote:
Hi
On Mon, May 12, 2014 at 12:26 PM, Sharma, Shashank
wrote:
Benefits of using color manager:
1. Unique framework for all the col
Hi
On Mon, May 12, 2014 at 12:26 PM, Sharma, Shashank
wrote:
> Benefits of using color manager:
>
> 1. Unique framework for all the color correction properties, across all
>DRM drivers, across various platforms.
> 2. Only one set/get call for all kind of prope
On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote:
> From: Chon Ming Lee
>
> The additional DPLL registers added to support Port D. Besides, add
> some new PHY control and status registers based on B-spec.
>
> v2: Based on Ville review
> - Corrected DPIO_PHY_STATUS of
On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote:
> From: Chon Ming Lee
>
> CHV has 2 display phys. First phy (IOSF offset 0x1A) has two channels,
> and second phy (IOSF offset 0x12) has single channel. The first phy is
> used for port B and port C, while second phy is onl
On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote:
> From: Chon Ming Lee
>
> Cherryview has 3 pipes. Some of the pll dpio offset calculation is
> based on pipe number. Need to use vlv_pipe_to_channel to calculate the
> correct phy channel to use for the pipe.
>
> Signed-of
2014-05-11 18:49 GMT+02:00 Daniel Vetter :
> On Sat, May 10, 2014 at 10:52 AM, Jörg Otte wrote:
>>> On Fri, May 09, 2014 at 05:14:38PM +0100, Damien Lespiau wrote:
On Fri, May 09, 2014 at 06:11:37PM +0200, Jörg Otte wrote:
> > Jörg, can you please boot with drm.debug=0xe, reproduce the i
On Mon, May 12, 2014 at 10:30:11AM +, Mateo Lozano, Oscar wrote:
> > Did you consider my alternative fix of restoring the old value in the error
> > path?
>
> Is that directed to Daniel or me? Restoring the old value is way easier, but
> I thought you wanted to keep is_pin_display as a theor
Add a function to stop and fail a test after the specified number of
seconds have elapsed.
Signed-off-by: Thomas Wood
---
lib/igt_core.c | 44 +---
lib/igt_core.h | 2 ++
2 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/lib/igt_core.c b/lib
Signed-off-by: Thomas Wood
---
lib/igt_debugfs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 4fd2e5a..0912f5b 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -459,7 +459,10 @@ static bool read_one_crc(igt_pipe_crc_t *pipe_crc,
igt_
-
Intel Corporation (UK) Limited
Registered No. 1134945 (England)
Registered Office: Pipers Way, Swindon SN3 1RJ
VAT No: 860 2173 47
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Mo
On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
> Adding relevant read out comparison code, in check_crtc_state, for the new
> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
> values for a DP downclock mode (if available). Suggested by Daniel.
>
> v2: Chang
Hello Daniel,
Please find the actual problem statement and design overview :
==
1. There are different color correction methods, supported by various
SOCs, across various platforms.
2. These properties vary platform-by-platform, dr
On Mon, May 12, 2014 at 09:05:45AM +, Mateo Lozano, Oscar wrote:
> Hi Daniel,
>
> Sorry, this fell through the cracks:
>
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Gracefully handle obj not bound
> > to
> > GGTT in is_pin_display
> >
> > On Wed, Apr 02, 2014 at 07:21:01PM +0100, oscar.m
Hi Daniel,
Sorry, this fell through the cracks:
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Gracefully handle obj not bound to
> GGTT in is_pin_display
>
> On Wed, Apr 02, 2014 at 07:21:01PM +0100, oscar.ma...@intel.com wrote:
> > From: Oscar Mateo
> >
> > Otherwise, we do a NULL pointer deref
On Mon, May 12, 2014 at 06:24:57PM +1000, Dave Airlie wrote:
> >>
> >> If we decide to go for property documentation inside the source code then I
> >> believe we'll have to create our own format, as creating a properties table
> >> from kerneldoc information extracted from comments is probably not
On 05/04/2014 03:22 PM, Chris Wilson wrote:
> 32b * 32b = 32b
>
> n = (u64)level * freq; to avoid overflow as you claim.
Updated patch to fix this problem is here, thanks!
>From a0f41a92d949c814c203672ff7efe219a90ca6df Mon Sep 17 00:00:00 2001
From: Aaron Lu
Date: Mon, 28 Apr 2014 11:02:52 +08
Re-adding dri-devel, all drm core stuff must be discussed there.
But on the actual issue at hand I still don't understand what you're
trying to solve. You add a complete new set of properties, using Intel
names (pipes, planes) for some attributes which at first seems
completely redundant to all th
Hi, Ken,
Thanks for your patch.
But how do you release your driver on the HSW products? If can't LRI/LRM
from userspace batches, almost all of OpenCL application can't run.
So if I want to announce that the OpenCL driver support HSW, it must have a
way to load L3CTRLREG2 and L3CTRL
On 12 May 2014 16:46, Dave Airlie wrote:
> Hi,
>
> A repost of the current state of the displayport MST support for
> i915, mainly targetted the Lenovo docks.
Also in git at
http://cgit.freedesktop.org/~airlied/linux/log/?h=drm-i915-mst-support
Dave.
>>
>> If we decide to go for property documentation inside the source code then I
>> believe we'll have to create our own format, as creating a properties table
>> from kerneldoc information extracted from comments is probably not possible.
>
> Can comeone pick up the ball here and figure out what
On Mon, May 12, 2014 at 11:37:53AM +0530, Sagar Arun Kamble wrote:
> I support approach using docbook to start since there are not lot of
> properties. Laurent has ack'ed this one. Can we go ahead with this?
> http://lists.freedesktop.org/archives/intel-gfx/2014-March/041527.html
>
> Adding descri
On Sun, 11 May 2014, Daniel Vetter wrote:
> On Sun, May 11, 2014 at 11:02 AM, Dave Airlie wrote:
>> On 11 May 2014 18:28, Thomas Meyer wrote:
>>> Hi,
>>>
>>> 3.14.3 works as expected.
>>> 3.15-rc5 shows a strange behaviour: When resuming from ram the X server
>>> seems to be disfunctional.
>>>
>
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