On Wed, Apr 30, 2014 at 03:13:53PM +0300, Imre Deak wrote: > On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote: > > From: Chon Ming Lee <chon.ming....@intel.com> > > > > Added programming phy layer for CHV based on "Application note for 1273 > > CHV Display phy". > > > > v2: Rebase the code and do some cleanup. > > v3: Rework based on Ville review. > > -Fix the macro where the ch info need to swap, and add parens to ? > > operator. > > -Fix wrong bit define for DPIO_PCS_SWING_CALC_0 and > > DPIO_PCS_SWING_CALC_1 and rename for meaningful. > > -Add some comments for CHV specific DPIO registers. > > -Change the dp margin registery value to decimal to align with the > > doc. > > -Fix the not clearing some value in vlv_dpio_read before write again. > > -Create new hdmi/dp encoder function for chv instead of share with > > valleyview. > > v4: Rebase the code after rename the DPIO registers define and upstream > > change. > > Based on Ville review. > > -For unique transition scale selection, after Ville point out, look > > like the doc might wrong for the bit 26. Use bit 27 for ch0 and > > ch1. > > -Break up some dpio write value into two/three steps for readability. > > -Remove unrelated change. > > -Add some shift define for some registers instead just give the hex > > value. > > -Fix a bug where write to wrong VLV_TX_DW3. > > v5: Based on Ville review. > > - Move tx lane latency optimal setting from chv_dp_pre_pll_enable to > > chv_pre_enable_dp, and chv_hdmi_pre_pll_enable to > > chv_hdmi_pre_enable respectively. > > - Fix typo in one margin_reg_value for DP_TRAIN_VOLTAGE_SWING_400. > > - Clear DPIO_TX_UNIQ_TRANS_SCALE_EN for DP and HDMI. > > - Mask the old deemph and swing bits for hdmi. > > v6: Remove stub for pre_pll_enable for dp and hdmi. > > > > Signed-off-by: Chon Ming Lee <chon.ming....@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com> > > [vsyrjala: Don't touch panel power sequencing on DP] > > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Looks ok, so: > Reviewed-by: Imre Deak <imre.d...@intel.com> > > Some nitpicks follow, fixing them is optional.
Ok I've merged this, but I think the nitpicks are valid. Ville, can you please throw a quick follow-up patch on top to address these? Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
