Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-di
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and st
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is n
On Fri, Apr 04, 2014 at 04:12:09PM -0700, Jesse Barnes wrote:
> This always indicates a bug somewhere.
We keep turning this off because we hadn't fixed all the bugs - as we
try to wait on a dead pipe. Maybe this time we won't be inundated with
WARNs...
-Chris
--
Chris Wilson, Intel Open Source T
On Fri, Apr 04, 2014 at 04:12:08PM -0700, Jesse Barnes wrote:
> The reason for these is lost in the mists of time, and they don't seem
> to be necessary anymore, so drop them.
Separate these two. The first seems to indeed be a random wait, whereas
the second appears to be a misapplication of proce
On Fri, Apr 04, 2014 at 10:41:07PM -0700, Ben Widawsky wrote:
> I opted to do this instead of grabbing the context reference after
> eb_create since eb_create can potentially call the shrinker, and that
> makes things very complicated. This simple patch balances the ref count
> without requiring a
I opted to do this instead of grabbing the context reference after
eb_create since eb_create can potentially call the shrinker, and that
makes things very complicated. This simple patch balances the ref count
without requiring a great deal of review to make sure the shrinker path
is safe.
Theoreti
This only applies to external sinks.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7642415..df7cc11 100644
--- a/drivers/gpu/drm/i91
Some platforms may not have it, and enumerating it is both confusing and
time consuming due to the hotplug and DDC probing.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.
This is supposed to fix some eDP PPS issues on some platforms.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 98cf24f..34d01be 100
The reason for these is lost in the mists of time, and they don't seem
to be necessary anymore, so drop them.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
i
The spec changed the order awhile back to put the ports at the end
again, but we never updated. Things seem to work ok either way, but
apparently there are some failures fixed by the new order, so let's just
go ahead and do it.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 2
This always indicates a bug somewhere.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6a6406f..c039f34 100644
--- a/drivers
Needs to happen after clock is running or it doesn't behave correctly.
v2: fix subject (Ville)
make it clearer that this occurs in pre_enable (Paulo)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_hdmi.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
2014-04-04 18:38 GMT-03:00 Jesse Barnes :
> Needs to happen after clock is running or it doesn't behave correctly.
>
> v2: fix subject (Ville)
> make it clearer that this occurs in pre_enable (Paulo)
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 18
Needs to happen after clock is running or it doesn't behave correctly.
v2: fix subject (Ville)
make it clearer that this occurs in pre_enable (Paulo)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_hdmi.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
2014-03-07 13:32 GMT-03:00 :
> From: Ville Syrjälä
>
> Sprite LP2+ registers don't exist on ILK/SNB so don't read them.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --
2014-04-02 14:08 GMT-03:00 Jesse Barnes :
> Needs to happen after clock is running or it doesn't behave correctly.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_hdmi.c |6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel
On Wed, Apr 02, 2014 at 10:08:51AM -0700, Jesse Barnes wrote:
> In case we end up bouncing these around between ports.
>
> Signed-off-by: Jesse Barnes
Whoops. Almost missed this one. I must have an spam filter for cover
letters in my brain or something,
Reviewed-by: Ville Syrjälä
> ---
> dri
[Disclaimer: I'm not familiar with this list. I tried to study FAQs but didn't
get much wiser. Please give pointers if I missed something that I should
have read before posting...]
I have a
00:02.0 VGA compatible controller: Intel Corporation Atom Processor
D4xx/D5xx/N4xx/N5xx Integrated Graphi
On Fri, Apr 04, 2014 at 02:41:00PM +0100, Chris Wilson wrote:
> On Fri, Apr 04, 2014 at 04:36:10PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > We don't do CPU access to GPU contexts so making the GPU access snoop
> > the CPU caches seems silly, and potentially expe
On Fri, Apr 04, 2014 at 04:24:05PM +0100, Chris Wilson wrote:
> On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > On Gen4+ platforms (except BDW), Render Cache Operational flush
> > cannot be enabled.
> > This WA is apparently required for all Ge
On Fri, Apr 04, 2014 at 06:35:21PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 04, 2014 at 04:24:05PM +0100, Chris Wilson wrote:
> > On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gu...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > On Gen4+ platforms (except BDW), Render Cache Operational f
On Fri, Apr 04, 2014 at 04:24:05PM +0100, Chris Wilson wrote:
> On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > On Gen4+ platforms (except BDW), Render Cache Operational flush
> > cannot be enabled.
> > This WA is apparently required for all Ge
On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> On Gen4+ platforms (except BDW), Render Cache Operational flush
> cannot be enabled.
> This WA is apparently required for all Gen4+ platforms,except BDW.
> In BDW, the bit has been repurposed otherwise.
Hi all,
New -testing cycle with cool stuff:
- cmd parser for gen7 but only in enforcing and not yet granting mode - the
batch copying stuff is still missing. Also performance is a bit ... rough
(Brad Volkin + OACONTROL fix from Ken).
- deprecate UMS harder (i.e. CONFIG_BROKEN)
- interrupt rewo
Hi Dave,
Merge window -fixes pull request as usual. Well, I did sneak in Jani's
drm_i915_private_t typedef removal, need to have fun with a big sed job
too ;-)
Otherwise:
- hdmi interlaced fixes (Jesse&Ville)
- pipe error/underrun/crc tracking fixes, regression in late 3.14-rc (but
not cc: stab
On Fri, Apr 04, 2014 at 04:36:10PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We don't do CPU access to GPU contexts so making the GPU access snoop
> the CPU caches seems silly, and potentially expensive.
>
> v2: Use !IS_VALLEYVIEW instead of HAS_LLC as this is really
If we always initialize kref for the context, even if we are using fake
contexts for hangstats when there is no hw support, we can forgo the
dance to dereference the ctx->obj and inspect whether we are permitted
to use kref inside i915_gem_context_reference() and _unreference().
My ulterior motive
From: Ville Syrjälä
We don't do CPU access to GPU contexts so making the GPU access snoop
the CPU caches seems silly, and potentially expensive.
v2: Use !IS_VALLEYVIEW instead of HAS_LLC as this is really
about what the PTEs can represent.
Add a comment clarifying the situation.
Signed-
On Fri, Apr 04, 2014 at 12:12:35PM +0100, Damien Lespiau wrote:
> On Thu, Mar 27, 2014 at 06:00:11PM +, oscar.ma...@intel.com wrote:
> > +int gen8_switch_context_queue(struct intel_engine *ring,
> > + struct i915_hw_context *to,
> > + u32 tail)
>
On Thu, Apr 03, 2014 at 05:28:54PM +0200, Daniel Vetter wrote:
> On Thu, Apr 03, 2014 at 01:21:38PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 03, 2014 at 08:05:35AM +0100, Chris Wilson wrote:
> > > On Wed, Apr 02, 2014 at 10:30:23PM -0700, Ben Widawsky wrote:
> > > > We have been setting the bit
From: Akash Goel
On Gen4+ platforms (except BDW), Render Cache Operational flush
cannot be enabled.
This WA is apparently required for all Gen4+ platforms,except BDW.
In BDW, the bit has been repurposed otherwise.
This has been tested only on vlv.
v2: Corrected the code regarding the wrong usage
On Thu, Apr 03, 2014 at 10:12:14AM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> On Gen4+ platforms (except BDW), Render Cache Operational flush
> cannot be enabled.
> This WA is apparently required for all Gen4+ platforms,except BDW.
> In BDW, the bit has been repurposed otherwise.
On Apr-04-2014 4:25 PM, Jani Nikula wrote:
> On Fri, 04 Apr 2014, Vandana Kannan wrote:
>> From: Pradeep Bhat
>>
>> This patch and finds out the lowest refresh rate supported for the resolution
>> same as the fixed_mode.
>> It also checks the VBT fields to see if panel supports seamless DRRS or n
On Thu, Mar 27, 2014 at 06:00:11PM +, oscar.ma...@intel.com wrote:
> +int gen8_switch_context_queue(struct intel_engine *ring,
> + struct i915_hw_context *to,
> + u32 tail)
> +{
> + struct drm_i915_gem_request *req = NULL;
> + unsigned
On Fri, 04 Apr 2014, Vandana Kannan wrote:
> From: Pradeep Bhat
>
> This patch and finds out the lowest refresh rate supported for the resolution
> same as the fixed_mode.
> It also checks the VBT fields to see if panel supports seamless DRRS or not.
> Based on above data it marks whether eDP pan
On 27/03/2014 22:23, Chris Wilson wrote:
On Thu, Mar 27, 2014 at 03:28:26PM +, arun.siluv...@linux.intel.com wrote:
From: "Siluvery, Arun"
This patch series adds a new ioctl to resize a gem object.
I'm tired, but off the top of my head, I think you can do away with the
magic extension to
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-di
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is n
On Thu, Apr 03, 2014 at 09:44:43PM -0700, Ben Widawsky wrote:
> On Thu, Apr 03, 2014 at 08:06:30AM +0100, Chris Wilson wrote:
> > @@ -377,7 +374,7 @@ void i915_gem_context_reset(struct drm_device *dev)
> > if (ring->last_context == dctx)
> > continue;
> >
> > -
41 matches
Mail list logo
