On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > For disabling L3 clock gating we need to set bit 25 of MMIO
> > register 940c. Earlier this was being done by just writing 1
> > into bi
In wait for vblank use usleep_range, which will use hrtimers instead of
msleep. Using msleep(1~20) there are more chances of sleeping for 20ms.
Using usleep_range uses hrtimers and hence are precise, worst case will
trigger an interrupt at the higher/max timeout.
Change-log: On replacing msleep(1)
BZ: 178761
In wait for vblank use usleep_range, which will use hrtimers instead of
msleep. Using msleep(1~20) there are more chances of sleeping for 20ms.
Using usleep_range uses hrtimers and hence are precise, worst case will
trigger an interrupt at the higher/max timeout.
Change-log: On replaci
On Mon, 2014-03-24 at 18:47 +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 08:32:30PM +0200, Ville Syrjälä wrote:
> > On Mon, Mar 24, 2014 at 11:20:40AM +, Gupta, Sourab wrote:
> > > On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> > > > On Mon, Mar 24, 2014 at 12:19:19PM +0530, s
Added a property to enable user space to set aspect ratio for HDMI displays.
If there is no user specified value, then PAR_NONE/Automatic option is set
by default. User can select aspect ratio 4:3 or 16:9. The aspect ratio
selected by user would come into effect with a mode set.
Signed-off-by: Van
On Mon, Mar 24, 2014 at 07:41:17PM -0700, Ben Widawsky wrote:
> On Fri, Mar 21, 2014 at 12:41:53PM +, Chris Wilson wrote:
> > As Broadwell has an increased virtual address size, it requires more
> > than 32 bits to store offsets into its address space. This includes the
> > debug registers to t
On Fri, Mar 21, 2014 at 12:41:53PM +, Chris Wilson wrote:
> As Broadwell has an increased virtual address size, it requires more
> than 32 bits to store offsets into its address space. This includes the
> debug registers to track the current HEAD of the individual rings, which
> may be anywhere
On Mon, Mar 24, 2014 at 06:53:47PM +, Damien Lespiau wrote:
> Using uint64_t in that second member makes it aligned to 64bits, while
> the first member is only 32bits. We then had a 32bits hole in there!
>
> Found-by: Chris Wilson
> Cc: Ben Widawsky
> Cc: Rafael Barbalho
> Signed-off-by: Da
I am not clear why we've never enabled it by default for GEN7. Looking
at the git hostiry, it seems Rodrigo disabled it by default, and it's
never been turned on. Quite a few fixes have gone in over the past year,
and I think many of us are running this successfully.
If there is some reason we kno
On Mon, Mar 24, 2014 at 6:46 PM, Ben Widawsky wrote:
> On Mon, Mar 24, 2014 at 06:41:47PM -0700, Stéphane Marchesin wrote:
>> On Mon, Mar 24, 2014 at 6:21 PM, Ben Widawsky
>> wrote:
>> > I am not clear why we've never enabled it by default for GEN7. Looking
>> > at the git hostiry, it seems Rodri
On Mon, Mar 24, 2014 at 06:41:47PM -0700, Stéphane Marchesin wrote:
> On Mon, Mar 24, 2014 at 6:21 PM, Ben Widawsky
> wrote:
> > I am not clear why we've never enabled it by default for GEN7. Looking
> > at the git hostiry, it seems Rodrigo disabled it by default, and it's
> > never been turned on
When using HDMI, the 300MHz clock is legal, but when in DVI mode it's
definitely not. This causes issues when we send a 300MHz signal over a
DVI cable which is specced for 165MHz only. So when in DVI mode let's
limit the clock to 165MHz.
Signed-off-by: Stéphane Marchesin
---
drivers/gpu/drm/i915
On Mon, Mar 24, 2014 at 6:21 PM, Ben Widawsky
wrote:
> I am not clear why we've never enabled it by default for GEN7. Looking
> at the git hostiry, it seems Rodrigo disabled it by default, and it's
> never been turned on. Quite a few fixes have gone in over the past year,
> and I think many of us
I am not clear why we've never enabled it by default for GEN7. Looking
at the git hostiry, it seems Rodrigo disabled it by default, and it's
never been turned on. Quite a few fixes have gone in over the past year,
and I think many of us are running this successfully.
If there is some reason we kno
When PPGTT was disabled by default, the patch also prevented the user
from overriding this behavior via module parameter. Being able to test
this on arbitrary kernels is extremely beneficial to track down the
remaining bugs. The patch that prevented this was:
commit 93a25a9e2d67765c3092bfaac9b855d
On Mon, Mar 24, 2014 at 04:14:32PM -0700, Ausmus, James wrote:
> On Sat, Mar 22, 2014 at 4:34 AM, Daniel Vetter wrote:
> > On Fri, Mar 21, 2014 at 05:51:01PM -0700, Ben Widawsky wrote:
> >> Let's try this again. I've pushed a branch here:
> >> http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h
On Sat, Mar 22, 2014 at 4:34 AM, Daniel Vetter wrote:
> On Fri, Mar 21, 2014 at 05:51:01PM -0700, Ben Widawsky wrote:
>> Let's try this again. I've pushed a branch here:
>> http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=bdw-backports
>>
>> I need to re-review some of the merge conflicts fo
On Sat, Mar 22, 2014 at 06:52:25PM +0100, Daniel Vetter wrote:
> On Fri, Mar 21, 2014 at 07:33:59PM +0200, Mika Kuoppala wrote:
> > Hi,
> >
> > Daniel Vetter writes:
> >
> > > There's an entire pile of issues in here:
> > >
> > > - Use the main RING_HEAD register, not ACTHD. ACTHD points at the
On Mon, Mar 24, 2014 at 09:26:52PM +0200, Ville Syrjälä wrote:
> On Sat, Mar 15, 2014 at 08:23:22PM +0530, deepa...@linux.intel.com wrote:
> > From: Deepak S
> >
> > When we use different rps events for different platform or due to wa, we
> > mgiht end up doing (vs) everywahere. Insted of this, L
On Mon, Mar 24, 2014 at 07:45:56PM +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 12:36:23PM -0700, Ben Widawsky wrote:
> > On Thu, Mar 20, 2014 at 11:10:13AM +, Chris Wilson wrote:
> > > On Fri, Dec 06, 2013 at 02:11:55PM -0800, Ben Widawsky wrote:
> > > > static int gen6_ppgtt_init(str
On Mon, Mar 24, 2014 at 12:36:23PM -0700, Ben Widawsky wrote:
> On Thu, Mar 20, 2014 at 11:10:13AM +, Chris Wilson wrote:
> > On Fri, Dec 06, 2013 at 02:11:55PM -0800, Ben Widawsky wrote:
> > > static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> > > {
> > > +#define GEN6_PD_ALIGN (PAGE_
On Thu, Mar 20, 2014 at 11:10:13AM +, Chris Wilson wrote:
> On Fri, Dec 06, 2013 at 02:11:55PM -0800, Ben Widawsky wrote:
> > static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> > {
> > +#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
> > +#define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
On Sat, Mar 15, 2014 at 08:23:23PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> With RC6 enabled, BYT has an HW issue in determining the right
> Gfx busyness.
> WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
> on increasing/decreasing the freq. This logic will m
Deepak, this patch can use review. If you have time, can you please take
a look.
There were some rebase conflicts from the last version, so please make
sure to recheck carefully (since I think you did look before).
Thanks.
On Wed, Mar 19, 2014 at 06:31:17PM -0700, Ben Widawsky wrote:
> Almost al
On Sat, Mar 22, 2014 at 09:06:00PM +, Chris Wilson wrote:
> On Sat, Mar 22, 2014 at 11:42:17AM -0700, Ben Widawsky wrote:
> > On Thu, Mar 20, 2014 at 07:24:38AM +, Chris Wilson wrote:
> > > On Wed, Mar 19, 2014 at 06:31:14PM -0700, Ben Widawsky wrote:
> > > > Programming it outside of the r
On Sat, Mar 15, 2014 at 08:23:24PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> We are adding a module paramter to control rps boost. By default, we
> enable the boost for better performace. Based on the need (perf/power)
> we can either enable/disable.
>
> v2: Addressed rps defau
On Sat, Mar 15, 2014 at 08:23:22PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> When we use different rps events for different platform or due to wa, we
> mgiht end up doing (vs) everywahere. Insted of this, Let's use a variable
> in dev_priv to track the enabled PM interrupts
>
>
Even without enabling the ringbuffers to allow command execution, we can
still control the display engines to enable modesetting. So make the
ringbuffer initialization failure soft, and mark the GPU as wedged
instead.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 9 ++---
During module load, if we fail to initialise the rings, we abort the
load reporting EIO. However during resume, even though we report EIO as
we fail to reinitialize the ringbuffers, the resume continues and the
device is restored - albeit in a non-functional state. As we cannot
execute any commands
Using uint64_t in that second member makes it aligned to 64bits, while
the first member is only 32bits. We then had a 32bits hole in there!
Found-by: Chris Wilson
Cc: Ben Widawsky
Cc: Rafael Barbalho
Signed-off-by: Damien Lespiau
---
lib/gen8_render.h | 38 +++-
On Mon, Mar 24, 2014 at 08:32:30PM +0200, Ville Syrjälä wrote:
> On Mon, Mar 24, 2014 at 11:20:40AM +, Gupta, Sourab wrote:
> > On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> > > On Mon, Mar 24, 2014 at 12:19:19PM +0530, sourab.gu...@intel.com wrote:
> > > > From: Akash Goel
> > > >
On Mon, Mar 24, 2014 at 11:20:40AM +, Gupta, Sourab wrote:
> On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> > On Mon, Mar 24, 2014 at 12:19:19PM +0530, sourab.gu...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > Added a new rendering specific Workaround
> > > 'WaTlbInvalidateS
From: Akash Goel
Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
Gen7 platform as it is not required.
v2: Enhancing the scope of the patch to full Gen7 (Chris)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
Tested-by: Chris Wilson # ivb, hsw -Chris
---
drivers/gpu/drm/i
On Mon, Mar 24, 2014 at 05:55:22PM +, Gupta, Sourab wrote:
> On Mon, 2014-03-24 at 17:47 +, Chris Wilson wrote:
> > On Mon, Mar 24, 2014 at 11:00:05PM +0530, sourab.gu...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
> >
On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> For disabling L3 clock gating we need to set bit 25 of MMIO
> register 940c. Earlier this was being done by just writing 1
> into bit 25 and resetting all other bits.
> This patch modifies the routine t
On Mon, 2014-03-24 at 17:47 +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 11:00:05PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
> > VLV platform as it is not required.
> >
> > Signed-off-by: Akash Goel
>
On Mon, Mar 24, 2014 at 11:00:05PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
> VLV platform as it is not required.
>
> Signed-off-by: Akash Goel
I've been running with this on ivb and hsw, and have not yet seen a
d
From: Akash Goel
Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
VLV platform as it is not required.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer
From: Akash Goel
For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destro
From: Akash Goel
In Valleyview, Operational flush cannot be enabled on
BWG A0 [Errata BWT006]
v2: Corrected the code regarding the wrong usage of
MASKED_BIT_DISABLE (Chris)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915
From: Akash Goel
This workaround is needed on VLV for the HW context feature.
It is used after adding the mi_set_context command in ring buffer
for Hw context switch. As per the spec
"The software must send a pipe_control with a CS stall and a post sync
operation and then a dummy DRAW after every
From: Akash Goel
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
v2: Modified the WA comment (Ville)
v3: Added the vlv identifier with WA name (Damien)
v4: Reworked based o
From: Akash Goel
This patch Enables the bit for TLB invalidate in GFX Mode register
for Gen7.
According to bspec, When enabled this bit limits the invalidation
of the TLB only to batch buffer boundaries, to pipe_control
commands which have the TLB invalidation bit set and sync flushes.
If disab
From: Sourab Gupta
This patch series adds rendering specific HW workarounds for VLV platform.
These patches leads to stable behavior on VLV, especially
when playing 3D Apps, benchmarks.
This patch series consolidates the earlier patch set in a clean thread
and adds the in-patch changelogs which
On Mon, Mar 24, 2014 at 02:05:37PM +0200, Jani Nikula wrote:
> On Mon, 24 Mar 2014, Daniel Vetter wrote:
> > On Mon, Mar 24, 2014 at 10:22:59AM +0200, Jani Nikula wrote:
> >> On Mon, 24 Mar 2014, Daniel Vetter wrote:
> >> > Since
> >> >
> >> > commit 5c673b60a9b3b23486f4eda75c72e91d31d26a2b
> >>
On Mon, Mar 17, 2014 at 07:09:23PM +0200, Mika Kuoppala wrote:
> To gain more coverage on interface, default context and banning.
> As there is no proper reset support for gen <= 3, we only
> do limited interface testing on those.
>
> Signed-off-by: Mika Kuoppala
Applied, thanks for the test. An
On Mon, Feb 24, 2014 at 09:11:43PM +0530, sagar.a.kam...@intel.com wrote:
> From: Sagar Kamble
>
> With this patch we allow larger cursor planes of sizes 128x128
> and 256x256.
>
> v2: Added more precise check on size while setting cursor plane.
I've just noticed that we currently hardcode 64 p
On Fri, 21 Mar 2014, Daniel Vetter wrote:
> > So I am still seeing this with current Linus' tree rather regularly (but
> > it's not deterministic enough for a reliable bisect).
> >
> > Unfortunately I haven't received any patches to test; what do you propose?
> > Would reporting this on bugs.freed
From: Chris Wilson
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough contiguous space in the vma when bind
From: Chris Wilson
Since dma_buf_vunmap() procedes blithely on ignorant of whether the
driver failed to actually unmap the backing storage for the dma-buf, we
need to make a best-effort to do so. This involves not allowing
ourselves to be susceptible to signals causing us to leak the storage.
Th
This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
Here goes the update list in order for better reviewers assignment:
Patch drm/i915: Bring UP Power Wells before disabling RC6. - Reviewer:
Patch drm/i915: dma_buf
From: Deepak S
We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.
v2: updated commit message. (Daniel)
Signed-off-by: Deepak S
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --g
On Mon, 24 Mar 2014, Daniel Vetter wrote:
> On Mon, Mar 24, 2014 at 10:22:59AM +0200, Jani Nikula wrote:
>> On Mon, 24 Mar 2014, Daniel Vetter wrote:
>> > Since
>> >
>> > commit 5c673b60a9b3b23486f4eda75c72e91d31d26a2b
>> > Author: Daniel Vetter
>> > Date: Fri Mar 7 20:34:46 2014 +0100
>> >
>>
On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 12:19:19PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> > In this WA, before pipecontrol with TLB invalidate set, nee
On Mon, 2014-03-24 at 09:31 +, Daniel Vetter wrote:
> On Mon, Mar 24, 2014 at 12:19:20PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > This workaround is needed on VLV for the HW context feature.
> > It is used after adding the mi_set_context command in ring buffer
> > for
On Mon, 2014-03-24 at 09:35 +, Daniel Vetter wrote:
> On Mon, Mar 24, 2014 at 12:19:18PM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > This patch series adds rendering specific HW workarounds for VLV platform.
> > These patches leads to stable behavior on VLV, especially
On Thursday 20 March 2014 07:01 AM, Ben Widawsky wrote:
this leaves a temporarily awkward min_delay (the soft limit) with the
new min_freq (the hardware limit). It's fixed in the next patch.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.
On Thursday 20 March 2014 07:01 AM, Ben Widawsky wrote:
Introduced:
commit b8a5ff8d7c676a04e0da5ec16bb068dd39459042
Author: Jeff McGee
Date: Tue Feb 4 11:37:01 2014 -0600
drm/i915: Update rps interrupt limits
Cc: Jeff McGee
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_s
On Thursday 20 March 2014 07:01 AM, Ben Widawsky wrote:
It is tested and looking fairly stable now, so turn it on. It wasn't
intentionally turned off originally :P
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+
> Its not expected to be too long, we tend to get vblank every 16ms.
> With using usleep_range with min and max as 1-2ms, we have observed that this
> function consuming 4ms to 17ms.
> Having 10ms sleep timer, we might tend to be blocking for 6ms in some
> cases.(from the above data) Moreover 1
> > > Ok. But W is still just a random value we picked for being the
> > > mininum legal value for msleep(). So just usleep_range(500, 2000)
> > > or somesuch will be fine. We can rename W to CAN_SLEEP it that helps.
> >
> > We do use _wait_for directly from intel_dp.c with W == 10 to not retry
On Mon, Mar 24, 2014 at 09:34:35AM +, Murthy, Arun R wrote:
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> >> b/drivers/gpu/drm/i915/intel_drv.h
> >> index 44067bc..079280a 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -52,7 +52,7
On Mon, Mar 24, 2014 at 09:48:09AM +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 09:34:35AM +, Murthy, Arun R wrote:
> > >> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > >> b/drivers/gpu/drm/i915/intel_drv.h
> > >> index 44067bc..079280a 100644
> > >> --- a/drivers/gpu/drm/i915/inte
On Mon, Mar 24, 2014 at 09:34:35AM +, Murthy, Arun R wrote:
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> >> b/drivers/gpu/drm/i915/intel_drv.h
> >> index 44067bc..079280a 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -52,7 +52,7
On Mon, Mar 24, 2014 at 12:19:24PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> For VLV, disabling L3 clock gating- MMIO 940c[25] = 1
>
> Signed-off-by: Akash Goel
> Signed-off-by: Sourab Gupta
> ---
> drivers/gpu/drm/i915/intel_pm.c | 7 +--
> 1 file changed, 5 insertions(
On Mon, Mar 24, 2014 at 12:19:20PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> This workaround is needed on VLV for the HW context feature.
> It is used after adding the mi_set_context command in ring buffer
> for Hw context switch. As per the spec
> "The software must send a pipe
On Mon, Mar 24, 2014 at 12:19:18PM +0530, sourab.gu...@intel.com wrote:
> From: Sourab Gupta
>
> This patch series adds rendering specific HW workarounds for VLV platform.
> These patches leads to stable behavior on VLV, especially
> when playing 3D Apps, benchmarks.
>
> Though, the patch set wa
On Mon, Mar 24, 2014 at 12:19:21PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> This patch Enables the bit for TLB invalidate in GFX Mode register
> for Gen7.
>
> According to bspec, When enabled this bit limits the invalidation
> of the TLB only to batch buffer boundaries, to pi
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 44067bc..079280a 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -52,7 +52,7 @@
>> break; \
On Mon, Mar 24, 2014 at 12:19:23PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> In Valleyview, Operational flush cannot be enabled on
> BWG A0 [Errata BWT006]
>
> Signed-off-by: Akash Goel
> Signed-off-by: Sourab Gupta
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/
On Mon, Mar 24, 2014 at 12:19:19PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
> Store data commands.
>
> Signed-off-by: Akash Go
On Mon, Mar 24, 2014 at 12:19:20PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> This workaround is needed on VLV for the HW context feature.
> It is used after adding the mi_set_context command in ring buffer
> for Hw context switch. As per the spec
> "The software must send a pipe
On Mon, Mar 24, 2014 at 10:22:59AM +0200, Jani Nikula wrote:
> On Mon, 24 Mar 2014, Daniel Vetter wrote:
> > Since
> >
> > commit 5c673b60a9b3b23486f4eda75c72e91d31d26a2b
> > Author: Daniel Vetter
> > Date: Fri Mar 7 20:34:46 2014 +0100
> >
> > drm/i915: Don't enable display error interrupt
On Mon, 24 Mar 2014, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 01:43:38PM +0530, Arun R Murthy wrote:
>> In wait for vblank use usleep_range, which will use hrtimers instead of
>> msleep. Using msleep(1~20) there are more chances of sleeping for 20ms.
>> Using usleep_range uses hrtimers and he
When Fedora updated the Kernel package from 3.12 to 3.13 my notebook
stopped booting (Kernel freezes) when a 2560 x 1440 high res monitor
is attached. I have tried using 3.13.6 from kernel.org and the problem
persists. The problem can be partially solved by passing nomodeset to
Kernel which will ma
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 44067bc..079280a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -52,7 +52,7 @@
> break; \
>
On Mon, Mar 24, 2014 at 01:43:38PM +0530, Arun R Murthy wrote:
> In wait for vblank use usleep_range, which will use hrtimers instead of
> msleep. Using msleep(1~20) there are more chances of sleeping for 20ms.
> Using usleep_range uses hrtimers and hence are precise, worst case will
> trigger an i
On Mon, 24 Mar 2014, Daniel Vetter wrote:
> Since
>
> commit 5c673b60a9b3b23486f4eda75c72e91d31d26a2b
> Author: Daniel Vetter
> Date: Fri Mar 7 20:34:46 2014 +0100
>
> drm/i915: Don't enable display error interrupts from the start
>
> we don't enable underrun interrupts any more at takeover
In wait for vblank use usleep_range, which will use hrtimers instead of
msleep. Using msleep(1~20) there are more chances of sleeping for 20ms.
Using usleep_range uses hrtimers and hence are precise, worst case will
trigger an interrupt at the higher/max timeout.
Signed-off-by: Arun R Murthy
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