On Thu, Feb 13, 2014 at 11:10:00AM +0800, Xiang, Haihao wrote:
> On Tue, 2014-01-28 at 09:53 +0800, yakui.z...@intel.com wrote:
> > From: Zhao Yakui
> >
> > The Sampler/Constant cache is read-only. And it can't be used as
> > the target cache agent of WRITE message.
> >
> > Signed-off-by: Zhao
On Thu, 13 Feb 2014, Shobhit Kumar wrote:
> MIPI Block #52 which provides configuration details for the MIPI panel
> including dphy settings as per panel and tcon specs
>
> Block #53 gives information on panel enable sequences
>
> Signed-off-by: Shobhit Kumar
> ---
> drivers/gpu/drm/i915/intel_b
The parser extracts the config block(#52) and sequence(#53) data
and store in private data structures.
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_bios.c | 175 --
drivers/gpu/drm/i915/intel_bios.h |
MIPI Block #52 which provides configuration details for the MIPI panel
including dphy settings as per panel and tcon specs
Block #53 gives information on panel enable sequences
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_bios.c | 5 +-
drivers/gpu/drm/i915/intel_bios.h | 152 +
Hi,
To support a plethora of MIPI panels, the VBT has been enhanced to support
multiple panels in a generic manner. This involves adding one MIPI configuration
block (#52) which provide all panel specific configuration data along with the
dphy configuration information as per panel/tcon specs. Als
On Tue, 2014-01-28 at 09:53 +0800, yakui.z...@intel.com wrote:
> From: Zhao Yakui
>
> The Sampler/Constant cache is read-only. And it can't be used as
> the target cache agent of WRITE message.
>
> Signed-off-by: Zhao Yakui
> ---
> assembler/gram.y | 4
> 1 file changed, 4 deletions(-)
>
On Thu, Feb 13, 2014 at 12:14:15AM +, Chris Wilson wrote:
> On Wed, Feb 12, 2014 at 02:28:47PM -0800, Ben Widawsky wrote:
> > This patch converts insert_entries and clear_range, both functions which
> > are specific to the VM. These functions tend to encapsulate the gen
> > specific PTE writes.
On Wed, Feb 12, 2014 at 02:28:47PM -0800, Ben Widawsky wrote:
> This patch converts insert_entries and clear_range, both functions which
> are specific to the VM. These functions tend to encapsulate the gen
> specific PTE writes. Passing absolute addresses to the insert_entries,
> and clear_range w
> I built the latest git version of edid-decode,
> and I see it printing this info:
>
> Extended tag: video capability data block
> YCbCr quantization: No Data (0)
> RGB quantization: No Data (0)
>
> If I toggle that "RGB quantization" bit (if I can figure
> out which byte it is in :-)
On Wed, Feb 12, 2014 at 11:45:59PM +, Chris Wilson wrote:
> On Wed, Feb 12, 2014 at 02:28:48PM -0800, Ben Widawsky wrote:
> > - for (i = first_pte; i < last_pte; i++)
> > + for (i = which_pte; i < last_pte; i++) {
> > pt_vaddr[i] = scratch_pte;
> > +
On Wed, Feb 12, 2014 at 02:28:48PM -0800, Ben Widawsky wrote:
> - for (i = first_pte; i < last_pte; i++)
> + for (i = which_pte; i < last_pte; i++) {
> pt_vaddr[i] = scratch_pte;
> + num_entries--;
> + BUG_ON(num_
On Wed, Feb 12, 2014 at 11:19:24PM +, Damien Lespiau wrote:
> On Wed, Feb 12, 2014 at 02:28:50PM -0800, Ben Widawsky wrote:
> > I keep meaning to do this... by now almost the entire file has been
> > written by an Intel employee (including Daniel post-2010).
> >
> > Signed-off-by: Ben Widawsky
On Wed, Feb 12, 2014 at 02:28:50PM -0800, Ben Widawsky wrote:
> I keep meaning to do this... by now almost the entire file has been
> written by an Intel employee (including Daniel post-2010).
>
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
> 1 file changed, 1
On Wed, Feb 12, 2014 at 11:14:59PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> After playing around Sagar's primary plane rotation a bit, I decided that
> extending that to full pipe rotation would be nice. Chris also seemed to
> want that, but I'm not sure he does anymo
On Wed, 12 Feb 2014 23:07:15 +
Chris Wilson wrote:
> On Wed, Feb 12, 2014 at 12:26:29PM -0800, Jesse Barnes wrote:
> > + /* Find the largest fb */
> > + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
> > + intel_crtc = to_intel_crtc(crtc);
> > +
> > + i
On Wed, Feb 12, 2014 at 12:26:29PM -0800, Jesse Barnes wrote:
> + /* Find the largest fb */
> + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
> + intel_crtc = to_intel_crtc(crtc);
> +
> + if (!intel_crtc->active || !intel_crtc->plane_config.fb) {
> +
It can be corrected later and may be what was actually desired, but
generally isn't, so if we find nothing is enabled, let the core DRM fb
helper figure something out.
v2: free the array too (Jesse)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_fbdev.c | 26 ++
It can be corrected later and may be what was actually desired, but
generally isn't, so if we find nothing is enabled, let the core DRM fb
helper figure something out.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_fbdev.c | 24 ++--
1 file changed, 22 insertion
We assign the sarea_priv pointer only in the dma ioctl, which is
disallowed when kernel modesetting is enabled. So this is dead code.
Cc: Stéphane Marchesin
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 29 -
1 file changed, 29 deletions(-)
... past the check for DRIVER_MODESET. Avoids races with userspace
opening a master and our sarea setup.
Cc: Signed-off-by: Stéphane Marchesin
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_dma.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/d
Avoids surprises when userspace races open/closes against this.
Cc: Stéphane Marchesin
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/i
The previous allocation mechanism would get 2 contiguous allocations,
one for the page directories, and one for the page tables. As each page
table is 1 page, and there are 512 of these per page directory, this
goes to 1MB. An unfriendly request at best. Worse still, our HW now
supports 4 page dire
Simply to match the GEN8 style of PPGTT initialization, split up the
allocations and mappings. Unlike GEN8, we skip a separate dma_addr_t
allocation function, as it is much simpler pre-gen8.
With this code it would be easy to make a more general PPGTT
initialization function with per GEN alloc/map
I keep meaning to do this... by now almost the entire file has been
written by an Intel employee (including Daniel post-2010).
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gp
This will make the code more readable, and extensible which is needed
for upcoming feature work. Eventually, we'll do the same for init.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 59 -
1 file changed, 38 insertions(+), 21 deletions(
Create 3 clear stages in PPGTT init. This will help with upcoming
changes be more readable. The 3 stages are, allocation, dma mapping, and
writing the P[DT]Es
One nice benefit to the patches is that it makes 2 very clear error
points, allocation, and mapping, and avoids having to do any handling
a
This patch converts insert_entries and clear_range, both functions which
are specific to the VM. These functions tend to encapsulate the gen
specific PTE writes. Passing absolute addresses to the insert_entries,
and clear_range will help make the logic clearer within the functions as
to what's goin
Rebased series from what I submitted a while ago:
http://lists.freedesktop.org/archives/intel-gfx/2013-December/037815.html
It was mostly a clean rebase, but there were a couple of major conflicts which
I think I cleaned up properly, but extra eyes would be good.
As before, the last two are optio
This reverts commit 3a2ffb65eec6dbda2fd8151894f51c18b42c8d41.
Now that the code is fixed to use smaller allocations, it should be safe
to let the full GGTT be used on DW.
The testcase for this is anything which uses more than half of the GTT,
thus eclipsing the old limit.
Signed-off-by: Ben Wida
This cleanup is similar to the GEN8 cleanup (though less necessary).
Having everything split will make cleaning the initialization path error
paths easier to understand.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 26 +++---
1 file changed, 19 insert
Like cleanup in an earlier patch, the code becomes much more readable,
and easier to extend if we extract out helper functions for the various
stages of init.
Note that with this patch it becomes really simple, and tempting to begin
using the 'goto out' idiom with explicit free/fini semantics. I'v
This allows drivers to use them in custom initial_config functions.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/drm_fb_helper.c |6 --
include/drm/drm_fb_helper.h |6 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/driv
From: Ville Syrjälä
I'd prefer have the crtc "rotation" property rotate the entire crtc
(planes and all). So for that reason we'd need to come up with some
other name for the "rotate the primary plane only" property.
Originally I had though that omapdrm had already made the decision for
us, but
From: Ville Syrjälä
The cursor plane also supports 180 degree rotation. Add a new
"cursor-rotation" property on the crtc which controls this.
Unlike sprites, the cursor has a fixed size, so if you have a small
cursor image with the rest of the bo filled by transparent pixels,
simply flipping the
From: Ville Syrjälä
Allow rotation properties to have custom names.
TODO: maybe squash into "drm: Add drm_mode_create_rotation_property()"
Cc: Sagar Kamble
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_crtc.c | 3 ++-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/
From: Ville Syrjälä
We can pretend that we can rotate the entire pipe by rotating all the
planes and adjusting their positions appropriately. Add a "rotation"
property on the crtc which will do this.
The main upshot of doing the full pipe rotation instead of rotating all
the planes individually
From: Ville Syrjälä
drm_rotation_chain() can be used to combine the plane and crtc rotations
to calculate the total rotation for a specific plane.
Cc: Sagar Kamble
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_crtc.c | 42 ++
include/drm/drm_crtc
From: Ville Syrjälä
After playing around Sagar's primary plane rotation a bit, I decided that
extending that to full pipe rotation would be nice. Chris also seemed to
want that, but I'm not sure he does anymore :) But then I decided it's so
easy to implement that I can't leave it hanging. So here
In the future, we need to be able to specify per-pipe number of planes.
Let's start today!
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_dma.c | 14 +++---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 4 ++--
3 files changed,
Early at init time, we can try to read out the plane config structure
and try to preserve it if possible.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |3 ++
drivers/gpu/drm/i915/intel_display.c | 82 ++
drivers/gpu/drm/i915/intel_drv
The BIOS or boot loader will generally create an initial display
configuration for us that includes some set of active pipes and
displays. This routine tries to figure out which pipes and connectors
are active and stuffs them into the crtcs and modes array given to us by
the drm_fb_helper code.
T
On Wed, Feb 12, 2014 at 07:31:16PM +0200, Imre Deak wrote:
> On Wed, 2014-02-12 at 17:55 +0100, Daniel Vetter wrote:
> > Just a bit of polish which I hope will help me with massaging some
> > internal patches to use Imre's reworked pipestat handling:
> > - Don't check for underrun reporting or enab
This should allow BIOS fb inheritance to work on ILK+ machines too.
v2: handle tiled BIOS fbs (Kristian)
split out common bits (Jesse)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 67 ++
1 file changed, 67 insertions(+)
diff --git
This allows drivers to use them in custom initial_config functions.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/drm_fb_helper.c |6 --
include/drm/drm_fb_helper.h |6 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/driv
Read out the current plane configuration at init time into a new
plane_config structure. This allows us to track any existing
framebuffers attached to the plane and potentially re-use them in our
fbdev code for a smooth handoff.
v2: update for new pitch_for_width function (Jesse)
comment how
Retrieve current framebuffer config info from the regs and create an fb
object for the buffer the BIOS or boot loader left us. This should
allow for smooth transitions to userspace apps once we finish the
initial configuration construction.
v2: check for non-native modes and adjust (Jesse)
fi
On Wed, Feb 12, 2014 at 07:18:19PM +, Chris Wilson wrote:
> On Wed, Feb 12, 2014 at 10:55:07AM -0800, Ben Widawsky wrote:
> > On Wed, Feb 12, 2014 at 08:15:58AM +, Chris Wilson wrote:
> > Are you opposed to doing anything at context creation? pid reference
> > works for me too, or hold on t
On Wed, Feb 12, 2014 at 10:55:07AM -0800, Ben Widawsky wrote:
> On Wed, Feb 12, 2014 at 08:15:58AM +, Chris Wilson wrote:
> Are you opposed to doing anything at context creation? pid reference
> works for me too, or hold on to it with the request - I don't care.
I'm just don't feel that the is
For stolen pages, since it is verboten to access them directly on many
architectures, we have to read them through the GTT aperture. If they
are not accessible through the aperture, then we have to abort.
This was complicated by
commit 8b6124a633d8095b0c8364f585edff9c59568a96
Author: Chris Wilson
On Wed, Feb 12, 2014 at 11:02:34AM -0800, Ben Widawsky wrote:
> On Wed, Feb 12, 2014 at 08:25:58AM +, Chris Wilson wrote:
> > On Tue, Feb 11, 2014 at 05:57:19PM -0800, Ben Widawsky wrote:
> > > On Mon, Feb 10, 2014 at 04:30:49PM +0200, Mika Kuoppala wrote:
> > > > -static struct drm_i915_gem_re
On Wed, Feb 12, 2014 at 08:13:50AM +, Chris Wilson wrote:
> On Tue, Feb 11, 2014 at 06:32:24PM -0800, Ben Widawsky wrote:
> > > @@ -3234,7 +3241,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void
> > > *arg)
> > >*/
> > > spin_lock_irqsave(&dev_priv->irq_lock, irqflag
On Wed, Feb 12, 2014 at 08:25:58AM +, Chris Wilson wrote:
> On Tue, Feb 11, 2014 at 05:57:19PM -0800, Ben Widawsky wrote:
> > On Mon, Feb 10, 2014 at 04:30:49PM +0200, Mika Kuoppala wrote:
> > > -static struct drm_i915_gem_request *
> > > -i915_gem_find_first_non_complete(struct intel_ring_buff
On Wed, Feb 12, 2014 at 08:15:58AM +, Chris Wilson wrote:
> On Tue, Feb 11, 2014 at 06:07:09PM -0800, Ben Widawsky wrote:
> > I still like my solution which does the strcpy on context creation. Your
> > solution is deferred in the usual case since the hangcheck is
> > asynchronous. The process
2014-02-12 16:06 GMT-02:00 Ville Syrjälä :
> On Wed, Feb 12, 2014 at 03:02:13PM -0200, Paulo Zanoni wrote:
>> 2014-02-12 9:26 GMT-02:00 Ville Syrjälä :
>> > On Wed, Feb 12, 2014 at 01:13:17PM +0200, Ville Syrjälä wrote:
>> >> On Thu, Dec 19, 2013 at 07:12:31PM -0200, Paulo Zanoni wrote:
>> >> > Fro
From: Sagar Kamble
Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.
v2: Calculating linear/tiled offsets based on pipe source width and
height. Added 180 degree rotation support in ironlake_update_plane.
v3: Checking if CRTC is active before issueing
From: Sagar Kamble
Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.
v2: Calculating linear/tiled offsets based on pipe source width and
height. Added 180 degree rotation support in ironlake_update_plane.
v3: Checking if CRTC is active before issueing
On Wed, Feb 12, 2014 at 03:02:13PM -0200, Paulo Zanoni wrote:
> 2014-02-12 9:26 GMT-02:00 Ville Syrjälä :
> > On Wed, Feb 12, 2014 at 01:13:17PM +0200, Ville Syrjälä wrote:
> >> On Thu, Dec 19, 2013 at 07:12:31PM -0200, Paulo Zanoni wrote:
> >> > From: Paulo Zanoni
> >> >
> >> > When I forked hasw
On Wed, Feb 12, 2014 at 6:27 PM, Imre Deak wrote:
>> This breaks DP on my BYT, I get bad flicker with it. Reverting only this
>> one fixes the issue.
>
> Adding Vijay.
Dropped from dinq for now.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwl
On Mon, Feb 10, 2014 at 04:30:49PM +0200, Mika Kuoppala wrote:
> From: Chris Wilson
>
> + request = i915_gem_find_active_request(ring);
> + if (request) {
> + /* We need to copy these to an anonymous buffer as the simplest
> + * method to avoid being overwritten b
On Wed, 2014-02-12 at 17:55 +0100, Daniel Vetter wrote:
> Just a bit of polish which I hope will help me with massaging some
> internal patches to use Imre's reworked pipestat handling:
> - Don't check for underrun reporting or enable pipestat interrupts
> twice.
> - Frob the comments a bit.
> -
On Wed, 2014-02-12 at 19:24 +0200, Imre Deak wrote:
> On Fri, 2014-02-07 at 19:58 +0100, Daniel Vetter wrote:
> > On Fri, Feb 07, 2014 at 05:58:16PM +0200, Ville Syrjälä wrote:
> > > On Fri, Feb 07, 2014 at 08:43:12PM +0530, Vijay Purushothaman wrote:
> > > > B-spec says the FIFO total size is 512.
On Fri, 2014-02-07 at 19:58 +0100, Daniel Vetter wrote:
> On Fri, Feb 07, 2014 at 05:58:16PM +0200, Ville Syrjälä wrote:
> > On Fri, Feb 07, 2014 at 08:43:12PM +0530, Vijay Purushothaman wrote:
> > > B-spec says the FIFO total size is 512. So fix this to 512.
> > >
> > > Signed-off-by: Vijay Purus
Just a bit of polish which I hope will help me with massaging some
internal patches to use Imre's reworked pipestat handling:
- Don't check for underrun reporting or enable pipestat interrupts
twice.
- Frob the comments a bit.
- Do the iir PIPE_EVENT to pipe mapping explicitly with a switch. We
On Wed, Feb 12, 2014 at 5:52 PM, Ville Syrjälä
wrote:
>> drivers/gpu/drm/i915/i915_irq.c | 25 -
>> drivers/gpu/drm/i915/i915_reg.h | 4
>> 2 files changed, 20 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c
>> b/drivers/gpu/drm/i915
2014-02-12 9:26 GMT-02:00 Ville Syrjälä :
> On Wed, Feb 12, 2014 at 01:13:17PM +0200, Ville Syrjälä wrote:
>> On Thu, Dec 19, 2013 at 07:12:31PM -0200, Paulo Zanoni wrote:
>> > From: Paulo Zanoni
>> >
>> > When I forked haswell_crtc_enable I copied all the code from
>> > ironlake_crtc_enable. The
On Wed, Feb 12, 2014 at 05:21:06PM +0100, Daniel Vetter wrote:
> Just a bit of polish which I hope will help me with massaging some
> internal patches to use Imre's reworked pipestat handling:
> - Don't check for underrun reporting twice.
> - Frob the comments a bit.
> - Do the iir PIPE_EVENT to pi
On Wed, Feb 12, 2014 at 03:54:27PM +, Thomas Wood wrote:
> Ensure sub-tests can be listed correctly by doing any test setup within
> an igt_fixture block.
>
> Signed-off-by: Thomas Wood
Oops, I've missed some. Patch merged, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporati
Just a bit of polish which I hope will help me with massaging some
internal patches to use Imre's reworked pipestat handling:
- Don't check for underrun reporting twice.
- Frob the comments a bit.
- Do the iir PIPE_EVENT to pipe mapping explicitly with a switch. We
only have one place which does
On Wed, Jan 29, 2014 at 3:56 PM, Ville Syrjälä
wrote:
> I think once we get to working on D0i2, we'll need to move the PSR
> wakeup to happen from a workqueue since it essentially requires a
> full modeset. Even now in your code it's somewhat questionable
> since you're doing stuff like aux transf
2014-02-11 19:54 GMT-02:00 Daniel Vetter :
> On Tue, Feb 11, 2014 at 6:20 PM, Paulo Zanoni wrote:
>> 2014-02-11 15:09 GMT-02:00 Paulo Zanoni :
>>> 2014-02-11 13:44 GMT-02:00 Daniel Vetter :
On Tue, Feb 11, 2014 at 4:23 PM, Paulo Zanoni wrote:
>
> 2014-02-10 15:23 GMT-02:00 Daniel Vet
Ensure sub-tests can be listed correctly by doing any test setup within
an igt_fixture block.
Signed-off-by: Thomas Wood
---
tests/gem_evict_alignment.c | 7 ---
tests/gem_pwrite_pread.c| 4 ++--
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/tests/gem_evict_alignment.c b
Forgotten to cc interested people ..
-Daniel
On Wed, Feb 12, 2014 at 3:19 PM, Daniel Vetter wrote:
> Apparently there's a bit a need for more verbose output in testcases,
> mostly for debugging purposes. At least gem_reset_stats and pm_rps
> have a verbose mode.
>
> On top of that we're currently
Apparently there's a bit a need for more verbose output in testcases,
mostly for debugging purposes. At least gem_reset_stats and pm_rps
have a verbose mode.
On top of that we're currently not taking advantage of piglit's "warn"
state all that much. But I think it might be useful for testcases whi
On Wed, Feb 12, 2014 at 12:22:00PM +0530, sagar.a.kam...@intel.com wrote:
> From: Sagar Kamble
>
> Primary planes support 180 degree rotation. Expose the feature
> through rotation drm property.
>
> v2: Calculating linear/tiled offsets based on pipe source width and
> height. Added 180 degree ro
On Wed, Feb 12, 2014 at 02:15:18PM +0100, Daniel Vetter wrote:
> On Wed, Feb 12, 2014 at 1:45 PM, Ville Syrjälä
> wrote:
> > BTW another funky issue I noticed about the video= option is that if you
> > specify a mode that's not part of the set of modes added by
> > drm_add_modes_noedid(), then fbc
On Wed, Feb 12, 2014 at 1:45 PM, Ville Syrjälä
wrote:
> BTW another funky issue I noticed about the video= option is that if you
> specify a mode that's not part of the set of modes added by
> drm_add_modes_noedid(), then fbcon will happily use the specified mode,
> but when X starts the mode gets
On Wed, Feb 12, 2014 at 01:04:28PM +0100, Daniel Vetter wrote:
> On Wed, Feb 12, 2014 at 10:19:39AM +0100, Daniel Vetter wrote:
> > On Tue, Feb 11, 2014 at 03:28:58PM -0800, Jesse Barnes wrote:
> > > The BIOS or boot loader will generally create an initial display
> > > configuration for us that in
I'm trying to figure out which bits to flip in the
EDID info for my TV so that the Intel video driver
will be willing to use full RGB as soon as possible
(I get tired of thinking my eyes have gone bad
when I'm booting my system :-).
I built the latest git version of edid-decode,
and I see it print
On Wed, Feb 12, 2014 at 10:19:39AM +0100, Daniel Vetter wrote:
> On Tue, Feb 11, 2014 at 03:28:58PM -0800, Jesse Barnes wrote:
> > The BIOS or boot loader will generally create an initial display
> > configuration for us that includes some set of active pipes and
> > displays. This routine tries t
On Wed, Feb 12, 2014 at 01:13:17PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 19, 2013 at 07:12:31PM -0200, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > When I forked haswell_crtc_enable I copied all the code from
> > ironlake_crtc_enable. The last piece of the function contains a big
> > co
On Thu, Dec 19, 2013 at 07:12:31PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> When I forked haswell_crtc_enable I copied all the code from
> ironlake_crtc_enable. The last piece of the function contains a big
> comment with a call to intel_wait_for_vblank. After this fork, we
> rearrange
On Wed, 12 Feb 2014, Chris Wilson wrote:
> On Wed, Feb 12, 2014 at 11:05:40AM +0800, Aaron Lu wrote:
>> The ACPI table on ASUS UX302LA has more than 8 output devices under the
>> graphics controller device node. The problem is, the real active output
>> device, the LCD panel, is listed the last. T
On Wed, Feb 12, 2014 at 11:05:40AM +0800, Aaron Lu wrote:
> The ACPI table on ASUS UX302LA has more than 8 output devices under the
> graphics controller device node. The problem is, the real active output
> device, the LCD panel, is listed the last. The result is, the LCD's
> device id doesn't get
On Wed, Feb 12, 2014 at 12:22:00PM +0530, sagar.a.kam...@intel.com wrote:
> From: Sagar Kamble
>
> Primary planes support 180 degree rotation. Expose the feature
> through rotation drm property.
>
> v2: Calculating linear/tiled offsets based on pipe source width and
> height. Added 180 degree ro
On Tue, Feb 11, 2014 at 03:01:31PM -0800, Ben Widawsky wrote:
> On Tue, Feb 11, 2014 at 02:22:37PM -0800, Ben Widawsky wrote:
> > On Tue, Feb 11, 2014 at 02:11:04PM -0800, Ben Widawsky wrote:
> > > On Thu, Jan 30, 2014 at 02:38:17PM +0200, Ville Syrjälä wrote:
> > > > On Wed, Jan 29, 2014 at 11:55:
On Tue, Feb 11, 2014 at 03:29:01PM -0800, Jesse Barnes wrote:
> +/*
> + * Build an intel_fbdev struct using a BIOS allocated framebuffer, if
> possible.
> + * The core display code will have read out the current plane configuration,
> + * so we use that to figure out if there's an object for us to
On Tue, Feb 11, 2014 at 03:28:58PM -0800, Jesse Barnes wrote:
> The BIOS or boot loader will generally create an initial display
> configuration for us that includes some set of active pipes and
> displays. This routine tries to figure out which pipes and connectors
> are active and stuffs them in
On Tue, Feb 11, 2014 at 03:28:56PM -0800, Jesse Barnes wrote:
> We want to do this early on before we try to fetch the plane config,
> which depends on some of the pipe config state.
I think the crucial step here is actually the gem setup, more specifically
the stolen setup. If we don't do the fb
On Tue, Feb 11, 2014 at 05:57:19PM -0800, Ben Widawsky wrote:
> On Mon, Feb 10, 2014 at 04:30:49PM +0200, Mika Kuoppala wrote:
> > -static struct drm_i915_gem_request *
> > -i915_gem_find_first_non_complete(struct intel_ring_buffer *ring)
> > +struct drm_i915_gem_request *
> > +i915_gem_find_active
On Tue, Feb 11, 2014 at 06:07:09PM -0800, Ben Widawsky wrote:
> I still like my solution which does the strcpy on context creation. Your
> solution is deferred in the usual case since the hangcheck is
> asynchronous. The process could be long dead and gone.
I disliked your solution since there was
On Tue, Feb 11, 2014 at 06:32:24PM -0800, Ben Widawsky wrote:
> > @@ -3234,7 +3241,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void
> > *arg)
> > */
> > spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> > if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTER
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