On 1/29/2014 1:03 AM, Daniel Vetter wrote:
On Tue, Jan 28, 2014 at 08:02:56PM +0530, S, Deepak wrote:
On 1/27/2014 10:22 PM, Daniel Vetter wrote:
On Mon, Jan 27, 2014 at 09:35:06PM +0530, deepa...@intel.com wrote:
From: Deepak S
When we enter RC6 and GFX Clocks are off, the voltage remai
Almost all of it is reusable from the existing code. The primary
difference is we need to do even less in the interrupt handler, since
interrupts are not shared in the same way.
The patch is mostly a copy-paste of the existing snb+ code, with updates
to the relevant parts requiring changes to the
It wasn't ever used by the caller anyway with the exception of what we
show in sysfs.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bcbdac
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6acb429..ae59bd9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/dri
It is tested and looking fairly stable now, so turn it on. It wasn't
intentionally turned off originally :P
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/i
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 944b99c..6acb429 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i91
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 34cc898..deaaaf2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/inte
Everything can be overridden by module parameters, so don't confuse the
users that are using them.
We have RC6 turned on for all platforms which support it, but Ironlake,
so the need to explain the situation is no longer pressing.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c
We have a need for duplicated parsing of the RP_STATE_CAPS register (and
the setting of the associated fields). To reuse some code, we can
extract the function into a simple helper.
This patch also addresses the fact that we missed doing this for gen8,
something we should have done anyway.
This c
This patch series implements RC6 and RPS for Broadwell. Most of the work
had already been done with the initial merge of Broadwell support,
however, there were a couple of missed things, and enough stuff had
moved around. The big change is the addition of the interrupt handlers.
I am mostly intere
Programming it outside of the rp0-rp1 range is considered a programming
error. Since we do not know that the previous value would actually be in
the range, program something we've read from the hardware, and therefore
know will work.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.
At one time, we though all future platforms would have the deeper RC6
states. As it turned out, they killed it after Ivybridge, and began
using other means to achieve the power savings (the stuff we need to get
to PC7+).
The enable function was left in a weird state of odd corner cases as a
result
From: Jeff McGee
igt_wait_helper compliments igt_stop_helper and is used when helper
processes are expected to exit naturally.
Signed-off-by: Jeff McGee
---
lib/drmtest.c | 17 +
lib/drmtest.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/lib/drmtest.c b/lib/drmtest.c
From: Jeff McGee
Like subtest basic-api, but additionally requires that current
frequency is increasing to the configured maximum within reasonable
time since we are loaded.
Signed-off-by: Jeff McGee
---
tests/pm_rps.c | 29 +
1 file changed, 29 insertions(+)
diff
From: Jeff McGee
Jeff McGee (4):
pm_rps: New subtest min-max-config-idle
lib/drmtest: Add igt_wait_helper
pm_rps: Add load helper for loading gpu
pm_rps: New subtest min-max-config-loaded
lib/drmtest.c | 17 +
lib/drmtest.h | 1 +
tests/pm_rps.c | 200 ++
From: Jeff McGee
The load helper submits repeated dword store commands to keep the
gpu loaded while subtests running in the parent process check for
expected rps response.
Signed-off-by: Jeff McGee
---
tests/pm_rps.c | 140 +++--
1 file chang
From: Jeff McGee
Like subtest basic-api, but additionally requires that current
frequency is settling to the configured minimum within reasonable
time since we are idle.
Signed-off-by: Jeff McGee
---
tests/pm_rps.c | 31 ++-
1 file changed, 30 insertions(+), 1 delet
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on
v2: Wait psr enable with timeout and more subtest added.
v3: Add wait for v_blank leeting test more reliable and preparing to
add Baytrail per-pipe tests.
Signed-off-by: Rodrigo Vivi
---
tests/Android.mk | 1 +
tests/Makefile.sources | 1 +
tests/kms_psr_sink_crc.c | 514 ++
This patch allows system to safely recover after kms_psr_sink_crc check
or any other similar case that might fail when PSR is enabled.
Ville made and sent me this patch after noticing that primary plane enabled
bit was set during test case and unset after failure. What was causing a hard
and non-r
On Tue, Jan 28, 2014 at 06:17:00PM +0100, Daniel Vetter wrote:
> On Wed, Jan 8, 2014 at 7:43 PM, Ville Syrjälä
> wrote:
> >
> > The log looks fairly clear to me:
> >
> > 1. initially panel fitter is enabled on pipe B, and pipe B is outputting
> >to LVDS and VGA. Border is enabled.
> > 2. pipe
On Tue, Jan 28, 2014 at 12:39:40PM +, Chris Wilson wrote:
> On Tue, Jan 28, 2014 at 01:16:34PM +0200, Mika Kuoppala wrote:
> > Hi,
> >
> > I am working with a patchset [1] which, originally, aimed to fix
> > how we find out the guilty batches with ppgtt.
> >
> > But during the review it becam
On Tue, Jan 28, 2014 at 03:51:06PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 28, 2014 at 01:12:44PM +, Chris Wilson wrote:
> > On Tue, Jan 28, 2014 at 02:51:53PM +0200, ville.syrj...@linux.intel.com
> > wrote:
> > > drm/i915: Don't waste fences for scanout when not needed
> >
> > But it's g
On Tue, Jan 28, 2014 at 08:02:56PM +0530, S, Deepak wrote:
>
>
> On 1/27/2014 10:22 PM, Daniel Vetter wrote:
> >On Mon, Jan 27, 2014 at 09:35:06PM +0530, deepa...@intel.com wrote:
> >>From: Deepak S
> >>
> >>When we enter RC6 and GFX Clocks are off, the voltage remains higher
> >>than Vmin. When
On Tue, Jan 28, 2014 at 03:57:13PM +, C, Ramalingam wrote:
> Hi Daniel,
>
> Thanks for your valuable review. I found that Rodrigo has submitted a
> solution for the same issue just before mine. I am seeing that solution is
> aligning to the expectations.
> http://lists.freedesktop.org/archiv
During eviction, we are only considering how to free up space within the
current address space and not concerned with freeing up physical memory.
As such we need only skip nodes that pinned in the current VM and not
globally.
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Cc: Ben Widawsky
---
d
On Wed, Jan 8, 2014 at 7:43 PM, Ville Syrjälä
wrote:
>
> The log looks fairly clear to me:
>
> 1. initially panel fitter is enabled on pipe B, and pipe B is outputting
>to LVDS and VGA. Border is enabled.
> 2. pipe A gets enabled outputting to LVDS. This will overwrite the
>LVDS border bit
This series fixes: https://bugs.freedesktop.org/show_bug.cgi?id=73533
Tested-by: Rodrigo Vivi
On Sun, Jan 26, 2014 at 4:58 PM, Ben Widawsky wrote:
> On Fri, Jan 17, 2014 at 04:20:31PM +0200, Mika Kuoppala wrote:
>> As we seek the guilty one using request ordering and hangcheck
>> score, these w
On Fri, Jan 24, 2014 at 04:24:46PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 24, 2014 at 04:14:10PM +0200, Ville Syrjälä wrote:
> > On Fri, Jan 24, 2014 at 07:18:43PM +0530, sagar.a.kam...@intel.com wrote:
> > > From: Sagar Kamble
> > >
> > > This patch enables 180 degree rotation for primary and
Hi Daniel,
Thanks for your valuable review. I found that Rodrigo has submitted a solution
for the same issue just before mine. I am seeing that solution is aligning to
the expectations.
http://lists.freedesktop.org/archives/intel-gfx/2014-January/038749.html
So may be we can ignore this submiss
On Tue, Jan 28, 2014 at 04:13:52PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 28, 2014 at 02:24:42PM +0100, Daniel Vetter wrote:
> > On Wed, Jan 22, 2014 at 09:32:52PM +0200, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > WaApplyL3ControlAndL3ChickenMode is only li
On 1/27/2014 10:22 PM, Daniel Vetter wrote:
On Mon, Jan 27, 2014 at 09:35:06PM +0530, deepa...@intel.com wrote:
From: Deepak S
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPn, it might fail since the
Gfx clocks are down. So t
On Tue, Jan 28, 2014 at 03:13:34PM +0200, Jani Nikula wrote:
> On Mon, 27 Jan 2014, Daniel Vetter wrote:
> > Split out from Chris vma-bind rework.
>
> "simplify" does not explain to me *why* you can skip two checks in the
> code.
Because they are all repeated in i915_vma_unbind().
-Chris
--
Ch
On 1/27/2014 10:37 PM, Ville Syrjälä wrote:
On Mon, Jan 27, 2014 at 09:35:06PM +0530, deepa...@intel.com wrote:
From: Deepak S
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPn, it might fail since the
Gfx clocks are down. So t
On Tue, Jan 28, 2014 at 02:24:42PM +0100, Daniel Vetter wrote:
> On Wed, Jan 22, 2014 at 09:32:52PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > WaApplyL3ControlAndL3ChickenMode is only listed for IVB and HSW in
> > W/A database and BSpec.
> >
> > Signed-off-by: Vi
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pip
On 01/27/14 15:31, Ville Syrjälä wrote:
> On Mon, Jan 27, 2014 at 03:09:34PM +0200, Antti Koskipaa wrote:
>> +.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
>> +.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
>> +.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET
On Tue, Jan 28, 2014 at 01:12:44PM +, Chris Wilson wrote:
> On Tue, Jan 28, 2014 at 02:51:53PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > After staring at the scanout vs. fences situation a bit, I decided
> > to reduce our scanout fence usage a bit.
>
> I fee
Hi,
Can one of you guys review that patch from Joao? You're in a quite
better place than me to do it.
(Note: you don't have to wait until one garbage collects the patches on
the ml, people should find good review candidates if nothing happens for
too long).
Thanks,
--
Damien
On Thu, Jan 23, 2
On Wed, Jan 22, 2014 at 09:32:54PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> WaDisableRCZUnitClockGating was needed with early HSW steppings only.
>
> Signed-off-by: Ville Syrjälä
I couldn't make sense of this diff, my hsw clock_gating function here
doesn't seem to
On Mon, 27 Jan 2014, Daniel Vetter wrote:
> Apparently I've lost a game of chicken. For review I'd like to sign up Jani
> for
> the overall series and Ben to upgrade his ack on the actual bugfix to a full
> r-b.
I'd like someone else to look at patches 2, 3, 5 and 6.
BR,
Jani.
--
Jani Nikula
On Wed, Jan 22, 2014 at 09:32:52PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> WaApplyL3ControlAndL3ChickenMode is only listed for IVB and HSW in
> W/A database and BSpec.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 --
> 1 file change
On Mon, 27 Jan 2014, Daniel Vetter wrote:
> This is prep work for reworking the object_pin logic. Atm
> it still does a (now redundant) lookup of the vma. The next
> patch will fix this.
>
> Split out from Chris vma-bind rework.
Reviewed-by: Jani Nikula
> Cc: Chris Wilson
> Cc: Ben Widawsky
>
By exporting the ability to map user address and inserting PTEs
representing their backing pages into the GTT, we can exploit UMA in order
to utilize normal application data as a texture source or even as a
render target (depending upon the capabilities of the chipset). This has
a number of uses, w
On Tue, Jan 28, 2014 at 02:51:53PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> After staring at the scanout vs. fences situation a bit, I decided
> to reduce our scanout fence usage a bit.
I feel that is a glorious overreaction to a bug in another piece of
code, but now
On Mon, 27 Jan 2014, Daniel Vetter wrote:
> Split out from Chris vma-bind rework.
"simplify" does not explain to me *why* you can skip two checks in the
code.
BR,
Jani.
> Cc: Chris Wilson
> Cc: Ben Widawsky
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_drv.h | 10
On Mon, 27 Jan 2014, Daniel Vetter wrote:
> Split out from Chris vma-bind rework.
Reviewed-by: Jani Nikula
> Cc: Chris Wilson
> Cc: Ben Widawsky
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff
On Tue, 28 Jan 2014, Daniel Vetter wrote:
> Anything more than just one bool parameter is just a pain to read,
> symbolic constants are much better.
>
> Split out from Chris' vma-binding rework patch.
>
> v2: Undo the behaviour change in object_pin that Chris spotted.
>
> Cc: Chris Wilson
> Cc: B
From: Ville Syrjälä
Gen2 and gen3 require fences for tiled scanout, but gen4+ only require a
fence for FBC GTT modification tracking. Install a fence for scanout
only when it might actually be required.
This could potentially be optimized even further, but this seems like
a fair comporomise for
From: Ville Syrjälä
Sprites never need fences for scanout, so let's not waste them where not
needed.
Renamed stuff a bit so that we have a nice set of functions for pinning
scanout buffers. intel_pin_fb_obj() and intel_unpin_fb_obj() are now the
versions that don't add fences, are intel_pin_fenc
From: Ville Syrjälä
We pin and fence the object using intel_pin_fenced_fb_obj() but
just went ahead and unpinned it directly from the gtt. Make the
destruction symmetric by using intel_unpin_fenced_fb_obj().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_fbdev.c | 4 ++--
1 file c
From: Ville Syrjälä
After staring at the scanout vs. fences situation a bit, I decided
to reduce our scanout fence usage a bit.
Ville Syrjälä (3):
drm/i915: Don't waste fences on sprite buffers
drm/i915: Fix fence leaks if fbdev setup fails
drm/i915: Don't waste fences for scanout when not
On Mon, Jan 27, 2014 at 10:41:57PM +0100, Daniel Vetter wrote:
> On Mon, Jan 27, 2014 at 10:26 PM, Chris Wilson
> wrote:
> > On Mon, Jan 27, 2014 at 09:49:47PM +0100, Daniel Vetter wrote:
> >> Userspace can currently provoke this when e.g. trying to use a pinned
> >> scanout as a cursor or overla
Thanks for the clarification: Reviewed-by: Rodrigo Vivi
On Tue, Jan 28, 2014 at 10:11 AM, Rodrigo Vivi wrote:
> On Wed, Jan 22, 2014 at 5:32 PM, wrote:
>> From: Ville Syrjälä
>>
>> Signed-off-by: Ville Syrjälä
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> drivers/gpu/drm/i915/intel_
On Tue, Jan 28, 2014 at 01:16:34PM +0200, Mika Kuoppala wrote:
> Hi,
>
> I am working with a patchset [1] which, originally, aimed to fix
> how we find out the guilty batches with ppgtt.
>
> But during the review it became clear that I don't have a clear
> idea how the behaviour should be when mu
Nope, I had misunderstood that definition.. Thanks for the clarification.
Reviewed-by: Rodrigo Vivi
On Tue, Jan 28, 2014 at 10:29 AM, Ville Syrjälä
wrote:
> On Tue, Jan 28, 2014 at 10:18:48AM -0200, Rodrigo Vivi wrote:
>> For this and next one: According to wa_database this wa seems relevant
>>
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> WaDisableRCCUnitClockGating is only relevant for SNB.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --g
On Mon, Jan 27, 2014 at 04:46:59PM -0800, Ben Widawsky wrote:
> On Mon, Jan 27, 2014 at 02:20:14PM -0800, Kenneth Graunke wrote:
> > According to the latest documentation, any PIPE_CONTROL with the
> > "Command Streamer Stall" bit set must also have another bit set,
> > with five different options.
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> Only early VLV steppings needed thist. Should no longer be relevant.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 14 +++---
> 1 file changed, 3 insertions(+), 11
On Tue, Jan 28, 2014 at 10:18:48AM -0200, Rodrigo Vivi wrote:
> For this and next one: According to wa_database this wa seems relevant
> for all gt, right?
snb is called gt in w/a database language, or did you mean something else?
>
> On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> > From: Ville Syr
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> WaApplyL3ControlAndL3ChickenMode is only relevant to early HSW
> steppings..
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 --
> 1 file changed, 6 deletions(-)
>
> d
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> WaDisableRCZUnitClockGating was needed with early HSW steppings only.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --gi
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> Someone copy pasted the comment from the SNB code w/o reading it.
> We never actually implemented the workaround to disable RCPB unit
> clock gating on IVB. It would have been needed for early steppings
Offload some of the overgrown intel_display.c, which is by far our
biggest file. No functional changes.
v2: rebase
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile|1 +
drivers/gpu/drm/i915/intel_display.c | 128
drivers/gpu/drm/i915/intel_d
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> Can't find WaDisableRHWOOptimizationForRenderHang listed for VLV.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/d
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> Can't find WaDisableRHWOOptimizationForRenderHang listed for HSW.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/d
For this and next one: According to wa_database this wa seems relevant
for all gt, right?
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> WaDisableRCCUnitClockGating is only relevant for SNB.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 +-
In the past, it was possible to have multiple batches per request due to
a stray signal or ENOMEM. As a result we had to scan each active object
(filtered by those having the COMMAND domain) for the one that contained
the ACTHD pointer. This was then made more complicated by the
introduction of ppg
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> Can't find any mention of WaDisableVDSUnitClockGating ever being
> relevant for SNB. Remove it.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 ++
> 1 file changed, 2
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 6 ++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i9
I agree that spec is strange, but following the spec correctly result
for this and next patch would be only this:
if (IS_IVB_GT1(dev))
I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
- else
I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
_MASKED
On Mon, Jan 27, 2014 at 11:07:06PM -0800, Ben Widawsky wrote:
> v2: Rebased upon cleaned up error state
>
> Cc: Chris Wilson
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_drv.h | 9
> drivers/gpu/drm/i915/i915_gpu_error.c | 39
> +++
On Mon, Jan 27, 2014 at 11:07:05PM -0800, Ben Widawsky wrote:
> Chris:
> Do we also want to capture?
> GAC_ECO_BITS /* gen6,7 */
> GAM_ECOCHK /* gen6,7 */
> GAB_CTL /* gen6 */
> GFX_MODE /* gen6 */
>
> Requested-by: Chris Wilson
> Signed-off-by: Ben Widawsky
Reviewed-by: Chris Wilson
-C
On Mon, Jan 27, 2014 at 11:07:04PM -0800, Ben Widawsky wrote:
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_drv.h | 62 +++
> drivers/gpu/drm/i915/i915_gpu_error.c | 137
> +-
> 2 files changed, 99 insertions(+), 100 deletions(
On Mon, Jan 27, 2014 at 11:07:03PM -0800, Ben Widawsky wrote:
> This helps make an upcoming patch a bit more reviewable
>
> Signed-off-by: Ben Widawsky
Slightly less choatic. By itself this patch is just churn, but I think
it just about justifies itself in the next patch.
Reviewed-by: Chris Wil
On Mon, Jan 27, 2014 at 11:07:02PM -0800, Ben Widawsky wrote:
> Create logical sections in an attempt to clean up, and continue to keep
> future additions clean.
>
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 60
> +--
> 1 file ch
On Mon, Jan 27, 2014 at 11:07:01PM -0800, Ben Widawsky wrote:
> The code has become quite hairy. By relocating all the generic registers
> it will become more obvious where future ones should go. There is still
> admittedly a bit of confusion left for things like per ring registers.
>
> A subseque
On Tue, Jan 28, 2014 at 01:15:35PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 27, 2014 at 10:43:07PM +, Chris Wilson wrote:
> > As the VM do not track activity of objects and instead use a large
> > hammer to forcibly idle and evict all of their associated objects when
> > one is released, it is
If multiple rings are hung at the same time by two different
contexts, both should get get blamed for hanging the GPU.
Signed-off-by: Mika Kuoppala
---
tests/gem_reset_stats.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/tests/gem_reset_stats.c b/test
Hi,
I am working with a patchset [1] which, originally, aimed to fix
how we find out the guilty batches with ppgtt.
But during the review it became clear that I don't have a clear
idea how the behaviour should be when multiple rings encounter
a problematic batch at the same time.
The following i
On Mon, Jan 27, 2014 at 10:43:07PM +, Chris Wilson wrote:
> As the VM do not track activity of objects and instead use a large
> hammer to forcibly idle and evict all of their associated objects when
> one is released, it is possible for that to cause a recursion when we
> need to wait for free
A common issue we have is that retiring requests causes recursion
through GTT manipulation or page table manipulation which we can only
handle at very specific points. However, to maintain internal
consistency (enforced through our sanity checks on write_domain at
various points in the GEM object l
By exporting the ability to map user address and inserting PTEs
representing their backing pages into the GTT, we can exploit UMA in order
to utilize normal application data as a texture source or even as a
render target (depending upon the capabilities of the chipset). This has
a number of uses, w
lib/interval_tree.c provides a simple interface for an interval-tree
(an augmented red-black tree) but is only built when testing the generic
macros for building interval-trees. For drivers with modest needs,
export the simple interval-tree library as is.
v2: Lots of help from Michel Lespinasse to
This is a fairly hairy piece of API - the implications of transforming
an ordinary portion of process memory into asynchronous DMA arena for
the GPU opens up a can of worms regarding memory protection and
inter-process sharing. On the other hand, it is a distinct advantage of
UMA that we have faile
On Tue, Jan 28, 2014 at 10:10 AM, Goel, Akash wrote:
> Hi Daniel,
>
> Please let us know about this patch, will this be up-streamed.
1. I've just sent out the merge confirmation mail minutes ago.
2. Please _never_ drop mailing lists when poking me (or in general,
really). See the internally docum
Hi Dave,
Pile of -fixes all over the place. Lot's of cc: stable.
Only big thing is that we've dropped the preliminary hw support tag for
bdw - it seems to work. Which also means that I'll shovel a few more bdw
patches through -fixes, there's 5 w/a patches from Ken already on
intel-gfx.
Cheers, D
On Tue, Jan 28, 2014 at 08:22:32AM +, Chris Wilson wrote:
> On Tue, Jan 28, 2014 at 09:11:17AM +0100, Daniel Vetter wrote:
> > On Mon, Jan 27, 2014 at 10:43:07PM +, Chris Wilson wrote:
> > > As the VM do not track activity of objects and instead use a large
> > > hammer to forcibly idle and
On Tue, Jan 28, 2014 at 09:11:17AM +0100, Daniel Vetter wrote:
> On Mon, Jan 27, 2014 at 10:43:07PM +, Chris Wilson wrote:
> > As the VM do not track activity of objects and instead use a large
> > hammer to forcibly idle and evict all of their associated objects when
> > one is released, it is
On Tue, 28 Jan 2014, Daniel Vetter wrote:
> On Tue, Jan 28, 2014 at 09:57:57AM +0200, Jani Nikula wrote:
>> On Thu, 19 Dec 2013, Paulo Zanoni wrote:
>> > From: Paulo Zanoni
>> >
>> > Because we already do the wait in software: see
>> > ironlake_wait_backlight_on and ironlake_edp_wait_backlight_o
On Mon, Jan 27, 2014 at 11:07:00PM -0800, Ben Widawsky wrote:
> There are cases where we want to know if there is a full, or aliased
> PPGTT. Currently, in fact the only distinction we ever need to make is
> when we're using full PPGTT.
>
> This patch is simply to promote readability and clarify f
On Mon, Jan 27, 2014 at 10:43:07PM +, Chris Wilson wrote:
> As the VM do not track activity of objects and instead use a large
> hammer to forcibly idle and evict all of their associated objects when
> one is released, it is possible for that to cause a recursion when we
> need to wait for free
On Mon, Jan 27, 2014 at 04:30:41PM -0800, Jesse Barnes wrote:
> On Mon, 13 Jan 2014 16:24:45 +0530
> akash.g...@intel.com wrote:
>
> > From: Akash Goel
> >
> > The 'offset' field of the 'scatterlist' structure was wrongly
> > programmed with the offset value from the base of stolen area,
> > whe
On Tue, Jan 28, 2014 at 09:57:57AM +0200, Jani Nikula wrote:
> On Thu, 19 Dec 2013, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > Because we already do the wait in software: see
> > ironlake_wait_backlight_on and ironlake_edp_wait_backlight_off.
> >
> > For the "backlight on" delay, even BSp
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