DRM gets very mad when you request an object which occupies a partial
page. As a DRM driver, i915 never really wants to anger DRM, and would
always just want the rounding done for us.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 2 ++
1 file changed, 2 insertions(+)
diff --
On Thursday, January 23, 2014 11:21:01 AM Bjorn Helgaas wrote:
> On Wed, Jan 22, 2014 at 8:42 PM, Yijing Wang wrote:
> > Since acpi_evaluate_object() returns acpi_status and not plain int,
> > ACPI_FAILURE() should be used for checking its return value. Also
> > add some detailed debug info when a
Many times in the past we have concluded that the cause of the GPU hang
has been that the hw status page was stale, usually because the GPU and
CPU disagreed over the address of the page. Having stumbled across yet
another issue that seems to be related to the HWSP, it is time to
include that infor
Currently we report through our error state only the rings that have
been initialised (as detected by ring->obj). This check is done after
the GPU reset and ring re-initialisation, which means that the software
state may not be the same as when we captured the hardware error and we
may not print ou
From: Jeff McGee
The current frequency should reach the minimum frequency within a
reasonable time during idle.
v2: Not using forcewake for this particular subtest per Daniel's
suggestion.
Signed-off-by: Jeff McGee
---
tests/pm_rps.c | 22 ++
1 file changed, 18 inserti
From: Ville Syrjälä
On g4x there's just one video DIP, but there can be two HDMI/DVI
ports. Currently even a DVI monitor on another port can clobber
the infoframes meant for a real HDMI monitor on the other port.
Make sure we only ever send DIPs to one port. The first port with a
HDMI sink to ge
From: Ville Syrjälä
Add an encoder specific hook to be called alongside the crtc .off()
hook.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 5 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_d
From: Ville Syrjälä
We have a couple of switch cases to compute the port value for the
VIDEO_DIP_CTL register. Replace them with a simple macro.
We do lose a few BUG() calls, but many people may consider that
an improvement.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h |
From: Ville Syrjälä
I was readin the infoframe code a bit today, and noticed that g4x can't
transmit infoframes to more than one port, even though it can have two
HDMI/DVI ports.
So I decided to "fix" it by making it work on a first come, first served
basis. This at least makes it reasonable to
On Wed, Jan 22, 2014 at 5:21 PM, Olof Johansson wrote:
> On Wed, Jan 22, 2014 at 2:06 AM, Daniel Vetter wrote:
>> Hi Stephen,
>>
>> On Wed, Jan 22, 2014 at 4:04 AM, Stephen Rothwell
>> wrote:
>>> Hi all,
>>>
>>> Today's linux-next merge of the drm-intel tree got a conflict in
>>> drivers/gpu/dr
On Thu, Jan 23, 2014 at 06:25:26PM -0200, Rodrigo Vivi wrote:
> On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> > From: Ville Syrjälä
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/driv
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6c0a10a..0
On Thu, Jan 23, 2014 at 07:49:20PM +0100, Daniel Vetter wrote:
> On Thu, Jan 23, 2014 at 11:15:42AM -0600, Jeff McGee wrote:
> > On Thu, Jan 23, 2014 at 11:40:18AM +0100, Daniel Vetter wrote:
> > > On Tue, Jan 21, 2014 at 05:14:34PM -0600, jeff.mc...@intel.com wrote:
> > > > From: Jeff McGee
> > >
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_
Reviewed-by: Rodrigo Vivi
On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> From: Ville Syrjälä
>
> The w/a database lists both WaPsdDispatchEnable and
> WaDisablePSDDualDispatchEnable for VLV. They appear to be the same
> thing, so list both names.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/g
On Thu, Jan 23, 2014 at 04:49:07PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Since fixing the FBC locking is a bigger task that will take a while,
> I decided to pull all the simple fixes from my branch and post them
> right away.
>
> Some of these I've posted before,
Through a twisty and circuituous path it is possible to currently trick
the code into creating a default context and forgetting to pin it
immediately into the GGTT. (This requires a system using contexts without
an aliasing ppgtt, which is currently restricted to Baytrails machines
manually specify
Due to switch between console and graphics modes multiple psr_enable
call will be made. On such occasions, to avoid repeated psr_setup,
a flag called psr_setup_done is used.
On suspend-resume, panel goes for a power cycle. Hence PSR setup
should be redone to enable the PSR after suspend-resume.
So
On Thu, Jan 23, 2014 at 06:30:02PM +, Chris Wilson wrote:
> Through a twisty and circuituous path it is possible to currently trick
> the code into creating a default context and forgetting to pin it
> immediately into the GGTT. (This requires a system using contexts without
> an aliasing ppgtt
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on
This patch allows system to safely recover after kms_psr_sink_crc check
or any other similar case that might fail when PSR is enabled.
Ville made and sent me this patch after noticing that primary plane enabled
bit was set during test case and unset after failure. What was causing a hard
and non-r
On Thu, Jan 23, 2014 at 02:37:24PM -0200, Paulo Zanoni wrote:
> 2014/1/22 Jesse Barnes :
> > Forgot to convert to using the refclk variable when I added refclk
> > readout support, and Paulo noticed the resulting calculation was off due
> > to the way p & r are stored.
> >
> > Reported-by: Paulo Za
On Thu, Jan 23, 2014 at 11:15:42AM -0600, Jeff McGee wrote:
> On Thu, Jan 23, 2014 at 11:40:18AM +0100, Daniel Vetter wrote:
> > On Tue, Jan 21, 2014 at 05:14:34PM -0600, jeff.mc...@intel.com wrote:
> > > From: Jeff McGee
> > >
> > > The current frequency should reach the minimum frequency within
On Thu, 23 Jan 2014 18:30:02 +
Chris Wilson wrote:
> Through a twisty and circuituous path it is possible to currently trick
> the code into creating a default context and forgetting to pin it
> immediately into the GGTT. (This requires a system using contexts without
> an aliasing ppgtt, whi
From: Joao Santos
Changed TOP to ANDROID_BUILD_TOP to allow package to be compiled as part
of a top build; LIBDRM_PATH changed to PATH_LIBDRM because otherwise it
cannot be written to when in a top build (must be getting used in some
other makefile).
Issue: VIZ-3495
Signed-off-by: Joao Santos
Through a twisty and circuituous path it is possible to currently trick
the code into creating a default context and forgetting to pin it
immediately into the GGTT. (This requires a system using contexts without
an aliasing ppgtt, which is currently restricted to Baytrails machines
manually specify
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_suspend.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c
b/drivers/gpu/drm/i915/i915_suspend.c
index 8150fdc..641faee 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/
This patch allows system to safely recover after kms_psr_sink_crc check
or any other similar case that might fail when PSR is enabled.
Ville made and sent me this patch after noticing that primary plane enabled
bit was set during test case and unset after failure. What was causing a hard
and non-r
Signed-off-by: Rodrigo Vivi
---
tests/Android.mk | 1 +
tests/Makefile.sources | 1 +
tests/kms_sink_crc_basic.c | 201 +
3 files changed, 203 insertions(+)
create mode 100644 tests/kms_sink_crc_basic.c
diff --git a/tests/Android.mk
Different from core PSR implementation (i.e. Haswell and Broadwell)
Baytrail PSR can be enabled even when source is ok because it
provides way to inactivate PSR whenever any screen updated is done.
Baytrail also doesn't provide any kind of Performance Counters.
Signed-off-by: Rodrigo Vivi
---
te
v2: Wait psr enable with timeout and more subtest added.
Signed-off-by: Rodrigo Vivi
---
tests/Android.mk | 1 +
tests/Makefile.sources | 1 +
tests/kms_psr_sink_crc.c | 508 +++
3 files changed, 510 insertions(+)
create mode 100644 test
v2: Avoid more than one setup. Removing initialization
and trusting allocation. (By Paulo Zanoni).
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 6 ++
drivers/gpu/drm/i915/intel_drv.h | 1 -
3 files changed, 3
This debugfs interface will allow intel-gpu-tools test case
to verify if screen has been updated properly on cases like PSR.
v2: Accepted all Daniel's suggestions:
* grab modeset lock
* loop over connector and check DPMS on
* return errors
* use _eDP1 suffix for easy future extensi
On Thu, Jan 23, 2014 at 11:40:18AM +0100, Daniel Vetter wrote:
> On Tue, Jan 21, 2014 at 05:14:34PM -0600, jeff.mc...@intel.com wrote:
> > From: Jeff McGee
> >
> > The current frequency should reach the minimum frequency within a
> > reasonable time during idle. We hold forcewake to prevent inter
2014/1/22 Jesse Barnes :
> Forgot to convert to using the refclk variable when I added refclk
> readout support, and Paulo noticed the resulting calculation was off due
> to the way p & r are stored.
>
> Reported-by: Paulo Zanoni
> Signed-off-by: Jesse Barnes
Reviewed-by: Paulo Zanoni
Tested-by
From: Ville Syrjälä
The ILK/SNB docs don't really mention the the DPFC_HT_MODIFY bit.
CTG docs clearly state that it should be set only when tracking
back buffer modification in persistent mode. The bit is supposed
to be set by software after the first CPU modification to the
back buffer, and it
From: Ville Syrjälä
The ILK/SNB docs are a bit unclear what the persistent mode does, but
the CTG docs clearly state that it was meant to be used when we're
tracking back buffer modifications. We never do that, so leave it in
non-persistent mode.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/dr
From: Ville Syrjälä
Since fixing the FBC locking is a bigger task that will take a while,
I decided to pull all the simple fixes from my branch and post them
right away.
Some of these I've posted before, some others have seen a bit of action
by being in a public branch.
The FBC_FENCE_OFF change
From: Ville Syrjälä
We set up all the bits for DPFC_CONTROL but forgot to actually
write them to the register. Oops.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gp
From: Ville Syrjälä
We use nuking instead of render tracking on IVB+, so there's
no point in writing IVB_FBC_RT_BASE.
v2: Drop the IVB_FBC_RT_BASE write too
v3: Move the SNB stuff elsewhere, leaving only IVB+ here
Acked-by: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i
From: Ville Syrjälä
Having a 4 byte register at 0x321b seems unlikely as that's not
4 byte aligned. Since later platforms have more or less the same FBC
registers with new names, assume that FBC_FENCE_OFF is at 0x3218 just
like DPFC_FENCE_YOFF.
This feels like a simple typo in BSpec. 321Bh looks
From: Ville Syrjälä
We will anyway re-enable FBC normally after resume, so trying to save
and restore the register makes little sense.
We do need to preserve the FBC1 interval bits in FBC_CONTROL since
we only initialize them during driver load, and try to preserve them
after that.
v2: s/I915_H
From: Ville Syrjälä
On CTG and IVB+ we don't try to preserve any bits from the
DPFC_CONTROL register. Follow suit on ILK/SNB.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
From: Ville Syrjälä
The debug message telling FBC1 has been enabled is missing a newline.
Add it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm
From: Ville Syrjälä
Make the FBC plane macros take the plane as a parameter.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++-
drivers/gpu/drm/i915/intel_pm.c | 13 +
2 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c6e047e..a7af5b4 100644
--- a/drivers/gpu/dr
On Thu, Jan 23, 2014 at 11:50:38AM +0100, Daniel Vetter wrote:
> On Thu, Jan 23, 2014 at 12:13:41AM -0700, Todd Previte wrote:
> > Add new definitions for hotplug live status bits for VLV2 since they're
> > in reverse order from the gen4x ones.
> >
> > Changelog:
> > - Restored gen4 bit definition
On Thu, Jan 23, 2014 at 12:13:41AM -0700, Todd Previte wrote:
> Add new definitions for hotplug live status bits for VLV2 since they're
> in reverse order from the gen4x ones.
>
> Changelog:
> - Restored gen4 bit definitions
> - Added new definitions for VLV2
> - Added platform check for IS_VALLEY
On Tue, Jan 21, 2014 at 05:14:34PM -0600, jeff.mc...@intel.com wrote:
> From: Jeff McGee
>
> The current frequency should reach the minimum frequency within a
> reasonable time during idle. We hold forcewake to prevent interference
> from sleep states.
>
> Signed-off-by: Jeff McGee
> ---
> tes
On Wed, Jan 22, 2014 at 04:38:11PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 22, 2014 at 02:26:26PM +, Damien Lespiau wrote:
> > On Wed, Jan 22, 2014 at 02:36:08PM +0200, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > Add a few new debugfs files which allow ch
On Wed, Jan 22, 2014 at 10:41:05AM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Looks like filter-out macro gets silently unhappy about an undefined variable.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Damien Lespiau
and pushed. Thanks for the patch.
--
Damien
__
Date 23.1.2014 08:57, Takashi Iwai wrote:
> At Thu, 23 Jan 2014 06:35:12 +,
> Lin, Mengdong wrote:
>>
>>> -Original Message-
>>> From: Takashi Iwai [mailto:ti...@suse.de]
>>> Sent: Thursday, January 23, 2014 1:19 AM
>>> To: Daniel Vetter
>>> Cc: Lin, Mengdong; Barnes, Jesse; Zanoni, Pau
On Thu, Jan 23, 2014 at 8:57 AM, Takashi Iwai wrote:
>> Thanks for clarification!
>> Maybe we can add output info (eg. display port number) to the eld entries
>> under /proc/asound/cardx. Is it okay?
>
> It's possible, but the proc file is just a help. It can't be the
> API. For accessing the i
On Thu, Jan 23, 2014 at 7:07 AM, Jani Nikula
wrote:
> On Wed, 22 Jan 2014, Daniel Vetter wrote:
>> Just figured I'll comment on these two issues, patches themselves look
>> really nice \o/
>
> Look nice they do, but it also makes me a little sad that neither git
> grep nor my source code tagging
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