On Sun, Sep 29, 2013 at 08:27:50PM +0200, Daniel Vetter wrote:
> On Sun, Sep 29, 2013 at 8:15 PM, Chris Wilson
> wrote:
> > The current test for an attached enabled encoder fails if we have
> > multiple connectors aliased to the same encoder - both connectors
> > believe they own the enabled enco
On Thu, Oct 03, 2013 at 11:35:46AM -0700, Jesse Barnes wrote:
> DPIO needs to have common reset de-asserted on soft resets like boot and
> S3. In some cases, the BIOS will have done this for us, but it should
> be safe to do at runtime as well, as long as we do it when the pipes are
> otherwise of
for igt test case.
v2: remove trailing spaces and fix conflicts
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 128 +++-
drivers/gpu/drm/i915/i915_drv.h | 16 ++---
drivers/gpu/drm/i915/intel_dp.c | 35 +-
3 files changed,
DPIO needs to have common reset de-asserted on soft resets like boot and
S3. In some cases, the BIOS will have done this for us, but it should
be safe to do at runtime as well, as long as we do it when the pipes are
otherwise off.
v2: update bit name to match docs better (Ville)
reset after C
After merging the drm-intel tree into -next an x86 allmodconfig build fails
with:
In file included from include/linux/kobject.h:29:0,
from include/linux/cpufreq.h:16,
from drivers/gpu/drm/i915/intel_pm.c:28:
drivers/gpu/drm/i915/intel_pm.c: In function ‘intel_pm_i
On Tue, Oct 01, 2013 at 03:26:29PM -0300, Rodrigo Vivi wrote:
> for igt test case.
>
> Signed-off-by: Rodrigo Vivi
Tried to apply this but it conflicted. Then I've noticed that there's some
trailing whitespace ;-) Can you please rebase on dinq and resend?
-Daniel
> ---
> drivers/gpu/drm/i915/i
On Thu, Oct 03, 2013 at 01:31:26PM -0300, Rodrigo Vivi wrote:
> Power Well in use forces constantly PSR to exit.
> On recent Kernel I noticed that PSR Performance Counter was always 0
> indicating that PSR was never really achieved.
> By masking LPSP, PSR can work normally and save power on Haswell
On Thu, 3 Oct 2013 19:38:26 +0300
Ville Syrjälä wrote:
> On Fri, Sep 27, 2013 at 12:34:31PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> > > This fixes resume on my test platform, since I think some DPIO bits need
> > > recalibration.
> > >
> >
On Fri, Sep 27, 2013 at 12:34:31PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> > This fixes resume on my test platform, since I think some DPIO bits need
> > recalibration.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
> >
On Thu, Oct 03, 2013 at 11:16:17PM +0800, Chon Ming Lee wrote:
> During system boot up, by default, the power gate for render, media and
> display well still power gated. Normally, BIOS will turn off the power
> gate. In the BIOS-less system, the driver need to turn off the power
> gate very earl
Power Well in use forces constantly PSR to exit.
On recent Kernel I noticed that PSR Performance Counter was always 0
indicating that PSR was never really achieved.
By masking LPSP, PSR can work normally and save power on Haswell.
Two bugs had been raised with PSR flag enabled:
- "Screen flickers
On Thu, Oct 03, 2013 at 11:19:56AM -0500, Felipe Contreras wrote:
> On Thu, Oct 3, 2013 at 11:01 AM, Chris Wilson
> wrote:
> > Oh, TearFree. That explains it. I plan to fix that up very soon.
>
> Cool. Any idea why this happens only in this game, and only in that
> exact loading screen?
No. Jus
On Thu, Oct 3, 2013 at 11:01 AM, Chris Wilson wrote:
> On Thu, Oct 03, 2013 at 10:56:43AM -0500, Felipe Contreras wrote:
>> On Thu, Oct 3, 2013 at 4:15 AM, Chris Wilson
>> wrote:
>> > On Thu, Oct 03, 2013 at 04:09:32AM -0500, Felipe Contreras wrote:
>> >> On Thu, Oct 3, 2013 at 3:17 AM, Chris Wi
On Thu, Oct 3, 2013 at 4:15 AM, Chris Wilson wrote:
> On Thu, Oct 03, 2013 at 04:09:32AM -0500, Felipe Contreras wrote:
>> On Thu, Oct 3, 2013 at 3:17 AM, Chris Wilson
>> wrote:
>> > That will hopefully catch which path is consuming too much time
>>
>> This is what I got:
>>
>> restarting timeou
On Thu, Oct 3, 2013 at 3:17 AM, Chris Wilson wrote:
> On Thu, Oct 03, 2013 at 03:06:03AM -0500, Felipe Contreras wrote:
>> On Thu, Oct 3, 2013 at 2:36 AM, Chris Wilson
>> wrote:
>> > On Thu, Oct 03, 2013 at 01:29:29AM -0500, Felipe Contreras wrote:
>> >> It's nice to avoid X server crashes (by n
On Thu, Oct 3, 2013 at 2:36 AM, Chris Wilson wrote:
> On Thu, Oct 03, 2013 at 01:29:29AM -0500, Felipe Contreras wrote:
>> It's nice to avoid X server crashes (by not passing negative values to
>> select(3)).
>>
>> For more information:
>> http://article.gmane.org/gmane.comp.freedesktop.xorg.devel
It's nice to avoid X server crashes (by not passing negative values to
select(3)).
For more information:
http://article.gmane.org/gmane.comp.freedesktop.xorg.devel/37388
Signed-off-by: Felipe Contreras
---
src/sna/sna_accel.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/sna/sna_ac
On Thu, Oct 03, 2013 at 10:56:43AM -0500, Felipe Contreras wrote:
> On Thu, Oct 3, 2013 at 4:15 AM, Chris Wilson wrote:
> > On Thu, Oct 03, 2013 at 04:09:32AM -0500, Felipe Contreras wrote:
> >> On Thu, Oct 3, 2013 at 3:17 AM, Chris Wilson
> >> wrote:
> >> > That will hopefully catch which path
During system boot up, by default, the power gate for render, media and
display well still power gated. Normally, BIOS will turn off the power
gate. In the BIOS-less system, the driver need to turn off the power
gate very early during driver load.
v2: Move this to intel_uncore_sanitize to allow
On Thu, 3 Oct 2013, Daniel Vetter wrote:
> Can you please attach full dmesg from boot up to the first WARN with
> drm.debug=0xe? This really shouldn't happen and indicates a bug
> somewhere ...
A bit difficult ... I originally thought that it was reliably
reproducible, but now I didn't get it af
Can you please attach full dmesg from boot up to the first WARN with
drm.debug=0xe? This really shouldn't happen and indicates a bug
somewhere ...
Cheers, Daniel
On Thu, Oct 3, 2013 at 11:46 AM, Jiri Kosina wrote:
> During resume from hibernation, I started to see the warning below since
>
>
During resume from hibernation, I started to see the warning below since
commit b8f102e8bf71cacf33326360fdf9dcfd1a63925b
Author: Egbert Eich
Date: Fri Jul 26 14:14:24 2013 +0200
drm/i915: Add messages useful for HPD storm detection debugging (v2)
the system
On Thu, Oct 03, 2013 at 04:09:32AM -0500, Felipe Contreras wrote:
> On Thu, Oct 3, 2013 at 3:17 AM, Chris Wilson wrote:
> > That will hopefully catch which path is consuming too much time
>
> This is what I got:
>
> restarting timeout[2] (14, 0, 0)
> restarting timeout[0] (16, 0, 0)
> restarting
On Thu, Oct 03, 2013 at 03:06:03AM -0500, Felipe Contreras wrote:
> On Thu, Oct 3, 2013 at 2:36 AM, Chris Wilson wrote:
> > On Thu, Oct 03, 2013 at 01:29:29AM -0500, Felipe Contreras wrote:
> >> It's nice to avoid X server crashes (by not passing negative values to
> >> select(3)).
> >>
> >> For m
On Tue, Oct 01, 2013 at 03:04:01PM -0700, Jesse Barnes wrote:
> On Wed, 25 Sep 2013 17:34:57 +0100
> Chris Wilson wrote:
>
> > After applying wait-boost we often find ourselves stuck at higher clocks
> > than required. The current threshold value requires the GPU to be
> > continuously and comple
On Thu, Oct 03, 2013 at 01:29:29AM -0500, Felipe Contreras wrote:
> It's nice to avoid X server crashes (by not passing negative values to
> select(3)).
>
> For more information:
> http://article.gmane.org/gmane.comp.freedesktop.xorg.devel/37388
>
> Signed-off-by: Felipe Contreras
Thanks for th
On Wed, Oct 02, 2013 at 03:53:16PM -0700, Francisco Jerez wrote:
> Otherwise using any atomic memory operation will lock up the GPU due
> to a Haswell hardware bug.
>
> v2: Use the _MASKED_BIT_ENABLE macro. Drop drm parameter definition.
>
> Signed-off-by: Francisco Jerez
> Reviewed-by: Ben Wid
On Wed, Oct 02, 2013 at 03:32:25PM -0700, Ben Widawsky wrote:
> On Wed, Oct 02, 2013 at 03:06:00PM -0700, Francisco Jerez wrote:
> > Signed-off-by: Francisco Jerez
> > ---
> > include/drm/i915_drm.h | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/include/drm/i915_drm.h b/include/d
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