On Sun, Jul 14, 2013 at 08:30:09PM +0400, Konstantin Khlebnikov wrote:
> This patch fixes regression in power consumtion of sandy bridge gpu, which
> exists since v3.6 Sometimes after resuming from s2ram gpu starts thinking that
> it's extremely busy. After that it never reaches rc6 state.
>
> Bug
On Sun, Jul 14, 2013 at 09:56:45PM +0400, Konstantin Khlebnikov wrote:
> Daniel Vetter wrote:
> >On Sun, Jul 14, 2013 at 6:30 PM, Konstantin Khlebnikov
> > wrote:
> >>This patch fixes regression in power consumtion of sandy bridge gpu, which
> >>exists since v3.6 Sometimes after resuming from s2ra
On Thu, Jul 04, 2013 at 11:35:34PM +0200, Daniel Vetter wrote:
> At the moment we have the following interrupt enabling sequence:
> 1. irq preinstall hook
> 2. enabling the interrupt handler and calling irq postinstall hook
> 3. enable rps interrupts from the async work
>
> And the folliwing disab
On Sun, Jul 14, 2013 at 05:13:34PM -0700, Ben Widawsky wrote:
> On Sun, Jul 14, 2013 at 11:31:29PM +0200, Daniel Vetter wrote:
> > On Sun, Jul 14, 2013 at 01:55:20PM -0700, Ben Widawsky wrote:
> > > On Fri, Jul 12, 2013 at 10:43:26PM +0200, Daniel Vetter wrote:
> [snip]
>
> > >
> > > Maybe while
On Thu, Jul 04, 2013 at 11:47:44AM -0700, Ben Widawsky wrote:
> Signed-off-by: Ben Widawsky
Ok, I've slurped the entire series into dinq, with the exception of this
patch - I'm waiting for the jury to figure out whether we can do this in
userspace with cpuid or not. If not I think the commit mess
On Thu, Jul 04, 2013 at 11:02:05AM -0700, Ben Widawsky wrote:
> The eLLC cannot be determined by PCIID because as far as we know, even
> machines supporting eLLC may not have it enabled, or fused off or
> whatever. It's possible this isn't actually true, and at that point we
> can switch to a DEV_I
On Mon, Jul 15, 2013 at 09:54:35AM -0700, Ben Widawsky wrote:
> On Mon, Jul 15, 2013 at 03:23:00PM +0100, Damien Lespiau wrote:
> > On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote:
> > > +/* Cacheability Control is a 4-bit value. The low three bits are stored
> > > in *
> > > + * bits
On Mon, Jul 15, 2013 at 11:01:13PM +0100, Chris Wilson wrote:
> On Mon, Jul 15, 2013 at 05:23:35PM -0300, Rodrigo Vivi wrote:
> > On Mon, Jul 15, 2013 at 11:01 AM, Chris Wilson
> > wrote:
> > > On Thu, Jul 11, 2013 at 06:45:02PM -0300, Rodrigo Vivi wrote:
> > >> v2: prefer seq_puts to seq_printf
On Mon, Jul 15, 2013 at 05:21:12PM -0300, Rodrigo Vivi wrote:
> On Mon, Jul 15, 2013 at 11:00 AM, Chris Wilson
> wrote:
> > On Thu, Jul 11, 2013 at 06:45:01PM -0300, Rodrigo Vivi wrote:
> >> @@ -1602,6 +1611,26 @@ void intel_edp_psr_disable(struct intel_dp
> >> *intel_dp)
> >> DRM_
On Mon, Jul 15, 2013 at 08:35:43PM -0700, Ben Widawsky wrote:
> On Sat, Jul 13, 2013 at 11:33:22AM +0200, Daniel Vetter wrote:
> > On Fri, Jul 12, 2013 at 09:45:54PM -0700, Ben Widawsky wrote:
> > > As we plumb the code with more VM information, it has become more
> > > obvious that the easiest way
On Mon, Jul 15, 2013 at 09:00:54PM -0700, Ben Widawsky wrote:
> On Mon, Jul 15, 2013 at 08:35:43PM -0700, Ben Widawsky wrote:
> > To me, aliasing ppgtt is just a wart that doesn't fit well with
> > anything. As such, my plan was to hide as much of it as possible in ggtt
> > functions. Using some ki
On Mon, Jul 15, 2013 at 08:57:13PM -0700, Ben Widawsky wrote:
> So here is the plan summing up from this mail thread and the other
> one...
>
> I'm calling the series done until we get feedback from Chris on the
> eviction/shrinker code. Basically whatever he signs off on, I am willing
> to implem
I put those commits because in the moment that they have been pushed my
system crash, should I make the bug report in bugs.freedesktop.org or with
the one in the arch bugs, I'm fine?
2013/7/15 Ben Widawsky
> On Mon, 15 Jul 2013 21:59:09 -0600
> Oscar Dario Trujillo Tejada wrote:
>
> > Sorry ab
On Mon, 15 Jul 2013 21:59:09 -0600
Oscar Dario Trujillo Tejada wrote:
> Sorry about this but, I dont know a better place to send it
> please read the bug report that I put in archlinux bug tracker
>
> https://bugs.archlinux.org/task/36155?project=1&cat%5B0%5D=10&string=xf86-video-intel
>
I am
Sorry about this but, I dont know a better place to send it
please read the bug report that I put in archlinux bug tracker
https://bugs.archlinux.org/task/36155?project=1&cat%5B0%5D=10&string=xf86-video-intel
___
Intel-gfx mailing list
Intel-gfx@lists.fr
On Mon, Jul 15, 2013 at 08:35:43PM -0700, Ben Widawsky wrote:
> On Sat, Jul 13, 2013 at 11:33:22AM +0200, Daniel Vetter wrote:
> > On Fri, Jul 12, 2013 at 09:45:54PM -0700, Ben Widawsky wrote:
> > > As we plumb the code with more VM information, it has become more
> > > obvious that the easiest way
On Fri, Jul 12, 2013 at 06:46:51PM +0200, Daniel Vetter wrote:
> On Fri, Jul 12, 2013 at 08:46:48AM -0700, Ben Widawsky wrote:
> > On Fri, Jul 12, 2013 at 08:26:07AM +0200, Daniel Vetter wrote:
> > > On Thu, Jul 11, 2013 at 07:23:08PM -0700, Ben Widawsky wrote:
> > > > On Tue, Jul 09, 2013 at 09:15
On Sat, Jul 13, 2013 at 11:33:22AM +0200, Daniel Vetter wrote:
> On Fri, Jul 12, 2013 at 09:45:54PM -0700, Ben Widawsky wrote:
> > As we plumb the code with more VM information, it has become more
> > obvious that the easiest way to deal with bind and unbind is to simply
> > put the function pointe
On 07/15/2013 07:42 PM, Rafael J. Wysocki wrote:
> On Monday, July 15, 2013 10:36:15 AM Aaron Lu wrote:
>> On 07/13/2013 08:46 AM, Rafael J. Wysocki wrote:
>>> From: Rafael J. Wysocki
>>>
>>> According to Matthew Garrett, "Windows 8 leaves backlight control up
>>> to individual graphics drivers ra
On Fri, Jul 12, 2013 at 09:52:46PM +0100, Chris Wilson wrote:
> On Fri, Jul 12, 2013 at 01:37:28PM -0700, Ben Widawsky wrote:
> > On Fri, Jul 12, 2013 at 03:02:34PM +0100, Chris Wilson wrote:
> > > In theory, the different register blocks were meant to be only ever
> > > touched when holding either
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/i915_gem.c between commits 19b2dbde5732
("drm/i915: Restore fences after resume and GPU resets") from Linus' tree
and d18b96190342 ("drm/i915: Fix incoherence with fence updates on
Sandybridge+") from the
On Monday, July 15, 2013 05:06:09 PM Igor Gnatenko wrote:
> On Sat, 2013-07-13 at 02:46 +0200, Rafael J. Wysocki wrote:
[...]
>
> I can't build it. Where did I go wrong?
Probably nowhere, you tried to build the ACPI video driver as a module, that's
all. And you need to apply https://patchwork.
On Mon, Jul 15, 2013 at 05:13:27PM -0300, Rodrigo Vivi wrote:
> On Mon, Jul 15, 2013 at 11:03 AM, Chris Wilson
> wrote:
> >> + seq_puts(m, "PSR not supported on this platform\n");
> >> + return 0;
> >> + }
> >> +
> >> + psrctl = I915_READ(EDP_PSR_CTL);
> >
> > Miss
On Mon, Jul 15, 2013 at 10:58:57AM -0700, Ben Widawsky wrote:
> I am perfectly fine with dropping this patch, which I think solves the
> problem. I see no reason to go back to a 4k aligned alloc, do you?
It still introduces a fair amount of fragmentation - but you can argue
that we should be alloc
On Mon, Jul 15, 2013 at 05:23:35PM -0300, Rodrigo Vivi wrote:
> On Mon, Jul 15, 2013 at 11:01 AM, Chris Wilson
> wrote:
> > On Thu, Jul 11, 2013 at 06:45:02PM -0300, Rodrigo Vivi wrote:
> >> v2: prefer seq_puts to seq_printf detected by Paulo Zanoni.
> >> v3: PSR is disabled by default. Without u
PSR tracking engine in HSW doesn't detect automagically some directly copy area
operations through scanout so we will have to kick it manually and
reschedule it to come back to normal operation as soon as possible.
v2: Before PSR Hook. Don't force it when busy yet.
v3/v4: Solved small conflict.
v5
On Mon, Jul 15, 2013 at 11:01 AM, Chris Wilson wrote:
> On Thu, Jul 11, 2013 at 06:45:02PM -0300, Rodrigo Vivi wrote:
>> v2: prefer seq_puts to seq_printf detected by Paulo Zanoni.
>> v3: PSR is disabled by default. Without userspace ready it
>> will cause regression for kde and xdm users
>
>
On Mon, Jul 15, 2013 at 11:00 AM, Chris Wilson wrote:
> On Thu, Jul 11, 2013 at 06:45:01PM -0300, Rodrigo Vivi wrote:
>> @@ -1602,6 +1611,26 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
>> DRM_ERROR("Timed out waiting for PSR Idle State\n");
>> }
>>
>> +void intel_edp_ps
On Mon, Jul 15, 2013 at 11:03 AM, Chris Wilson wrote:
> On Thu, Jul 11, 2013 at 06:44:59PM -0300, Rodrigo Vivi wrote:
>> Adding support for PSR Status, PSR entry counter and performance counters.
>> Heavily based on initial work from Shobhit.
>>
>> v2: Fix PSR Status Link bits by Paulo Zanoni.
>>
2013/7/14 Chris Wilson :
> On Sun, Jul 14, 2013 at 12:42:49PM -0700, Ben Widawsky wrote:
>> On Fri, Jul 12, 2013 at 06:08:22PM +0100, Chris Wilson wrote:
>> > Currently, the register access code is split between i915_drv.c and
>> > intel_pm.c. It only bares a superficial resemblance to the reset of
On Mon, Jul 15, 2013 at 10:24:19AM -0700, Ben Widawsky wrote:
> On Mon, Jul 15, 2013 at 01:44:13PM +0100, Chris Wilson wrote:
> > On Sun, Jul 14, 2013 at 09:22:44AM -0700, Ben Widawsky wrote:
> > > Finally, in the series I reenable rc6 on ILK. I've never had an issue
> > > with this on my ILK, but
The medium term plan is to just use the existing context code on ILK as
well. The conversion just assists. Therefore, this is somewhat transient
as I plan to kill renderctx quite soon.
v2: Make NULL check style consistent (Chris)
Ditch superfluous 'else' (Chris)
Signed-off-by: Ben Widawsky
---
On Mon, Jul 15, 2013 at 11:30:15AM +0100, Chris Wilson wrote:
> On Sun, Jul 14, 2013 at 09:22:52AM -0700, Ben Widawsky wrote:
> > Now that I've killed renderctx, and the ILK pm code no longer has
> > anything shared with the regular i915 context code, make the pin
> > arguments the same as how they
On Mon, Jul 15, 2013 at 01:44:13PM +0100, Chris Wilson wrote:
> On Sun, Jul 14, 2013 at 09:22:44AM -0700, Ben Widawsky wrote:
> > Finally, in the series I reenable rc6 on ILK. I've never had an issue
> > with this on my ILK, but I recommend anyone testing on it who sees
> > issues to try to disable
On Mon, Jul 15, 2013 at 03:23:00PM +0100, Damien Lespiau wrote:
> On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote:
> > +/* Cacheability Control is a 4-bit value. The low three bits are stored in
> > *
> > + * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the
> > PT
On Sun, Jul 14, 2013 at 11:35:46PM +0200, Daniel Vetter wrote:
> On Sun, Jul 14, 2013 at 02:06:28PM -0700, Ben Widawsky wrote:
> > On Fri, Jul 12, 2013 at 10:43:27PM +0200, Daniel Vetter wrote:
> > > The VECS enabling required some changes to how rps interrupts are
> > > enabled/disabled since VECS
On Sat, 2013-07-13 at 02:46 +0200, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> According to Matthew Garrett, "Windows 8 leaves backlight control up
> to individual graphics drivers rather than making ACPI calls itself.
> There's plenty of evidence to suggest that the Intel driver for
>
Daniel Vetter wrote:
On Sun, Jul 14, 2013 at 6:30 PM, Konstantin Khlebnikov
wrote:
This patch fixes regression in power consumtion of sandy bridge gpu, which
exists since v3.6 Sometimes after resuming from s2ram gpu starts thinking that
it's extremely busy. After that it never reaches rc6 stat
This patch fixes regression in power consumtion of sandy bridge gpu, which
exists since v3.6 Sometimes after resuming from s2ram gpu starts thinking that
it's extremely busy. After that it never reaches rc6 state.
Bug was introduce by commit b4ae3f22d238617ca11610b29fde16cf8c0bc6e0
("drm/i915: loa
On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote:
> +/* Cacheability Control is a 4-bit value. The low three bits are stored in *
> + * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
> + */
> +#define HSW_CACHEABILITY_CONTROL(bits) bits) & 0x7) << 1)
On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote:
> From: Ben Widawsky
>
> The cacheability controls have changed, and the bits have been
> rearranged in general.
>
> v2: Remove comments for snb/ivb cache leves, that's a separate change.
>
> v3: Resolve conflicts due to patch series
On Thu, Jul 11, 2013 at 06:45:01PM -0300, Rodrigo Vivi wrote:
> @@ -1602,6 +1611,26 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
> DRM_ERROR("Timed out waiting for PSR Idle State\n");
> }
>
> +void intel_edp_psr_update(struct drm_device *dev)
> +{
> + struct intel_e
On Thu, Jul 11, 2013 at 06:45:00PM -0300, Rodrigo Vivi wrote:
> v2: Prefer seq_puts to seq_printf by Paulo Zanoni.
> v3: small changes like avoiding calling dp_to_dig_port twice as noticed by
> Paulo Zanoni.
> v4: Avoiding reading non-existent registers - noticed by Paulo
> on first psr deb
On Thu, Jul 11, 2013 at 06:44:59PM -0300, Rodrigo Vivi wrote:
> Adding support for PSR Status, PSR entry counter and performance counters.
> Heavily based on initial work from Shobhit.
>
> v2: Fix PSR Status Link bits by Paulo Zanoni.
> v3: Prefer seq_puts to seq_printf by Paulo Zanoni.
> v4: Fix
On Thu, Jul 11, 2013 at 06:45:02PM -0300, Rodrigo Vivi wrote:
> v2: prefer seq_puts to seq_printf detected by Paulo Zanoni.
> v3: PSR is disabled by default. Without userspace ready it
> will cause regression for kde and xdm users
I think we should still aim to enable by default and disable on
On Thu, Jul 11, 2013 at 06:45:04PM -0300, Rodrigo Vivi wrote:
> +static void intel_edp_psr_delayed_normal_work(struct work_struct *__work)
> +{
> + struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
> + struct intel_dp,
> +
On Sun, Jul 14, 2013 at 09:22:44AM -0700, Ben Widawsky wrote:
> Finally, in the series I reenable rc6 on ILK. I've never had an issue
> with this on my ILK, but I recommend anyone testing on it who sees
> issues to try to disable it via modparam firstly.
>
> The patch series is minimally tested. I
On Monday, July 15, 2013 10:36:15 AM Aaron Lu wrote:
> On 07/13/2013 08:46 AM, Rafael J. Wysocki wrote:
> > From: Rafael J. Wysocki
> >
> > According to Matthew Garrett, "Windows 8 leaves backlight control up
> > to individual graphics drivers rather than making ACPI calls itself.
> > There's ple
On Sun, Jul 14, 2013 at 09:22:44AM -0700, Ben Widawsky wrote:
> By the request of Ken, and Chris, I've added support for HW contexts to
> Ironlake. This is not the first time I've done this, but I think I'll
> skip the somewhat ugly history on the matter.
>
> Our existing support for Ironlake sets
On Sun, Jul 14, 2013 at 09:22:52AM -0700, Ben Widawsky wrote:
> Now that I've killed renderctx, and the ILK pm code no longer has
> anything shared with the regular i915 context code, make the pin
> arguments the same as how they were before I started.
>
> I do not know the reason for the original
On Sun, Jul 14, 2013 at 09:22:46AM -0700, Ben Widawsky wrote:
> @@ -3650,10 +3650,14 @@ static int ironlake_setup_rc6(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (dev_priv->ips.renderctx == NULL)
> - dev_priv->ips.renderctx =
On Friday 12 July 2013 03:14 AM, Rodrigo Vivi wrote:
I'm resending full series again because after accepting most of suggestions
and rebasing again on drm-intel-nightly most of patches got some kind of
conflict so the full series is here again.
First 3 patches on this series are already reviewed
Ben Widawsky writes:
> FWD'd from our internal list now that we have more insight.
> - Forwarded message from Ben Widawsky -
>
> Date: Thu, 11 Jul 2013 10:32:03 -0700
> From: Ben Widawsky
> To: linux-...@linux.intel.com
> Subject: intel_gpu_top broken for HSW. Ideas needed
> Message-ID:
53 matches
Mail list logo
