On Fri, May 31, 2013 at 02:46:20PM -0700, Ben Widawsky wrote:
> The way the stolen handling works is we take a pin on the backing pages,
> but we never actually get a reference to the bo. On freeing objects
> allocated with stolen memory, the final unref will end up freeing the
> object with pinned
2013/5/31 Paulo Zanoni :
> 2013/5/31 Daniel Vetter :
>> ... not the port clock. This allows us to kill the funny semantics
>> around pixel_target_clock.
>>
>> Since the dpll code still needs the real port clock, add a new
>> port_clock field to the pipe configuration. Handling the default case
>> f
2013/5/31 Daniel Vetter :
> ... not the port clock. This allows us to kill the funny semantics
> around pixel_target_clock.
>
> Since the dpll code still needs the real port clock, add a new
> port_clock field to the pipe configuration. Handling the default case
> for that one is a bit tricky, sinc
This should have been in reply to patch 2, sorry...
On Fri, May 31, 2013 at 02:46:19PM -0700, Ben Widawsky wrote:
> This makes it easier to catch leaks.
>
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> di
The way the stolen handling works is we take a pin on the backing pages,
but we never actually get a reference to the bo. On freeing objects
allocated with stolen memory, the final unref will end up freeing the
object with pinned pages count left. To enable an assertion to catch
bugs in this code p
This makes it easier to catch leaks.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 89cbfab..bc593e3 100644
--- a/dri
Hi Ville,
Thanks for the comments.
On Fri, May 31, 2013 at 12:59 PM, Ville Syrjälä
wrote:
> On Tue, May 28, 2013 at 09:25:12PM -0300, Rodrigo Vivi wrote:
>> WaFbcNukeOn3DBlt for IVB, HSW and VLV.
>
> VLV doesn't have FBC, so this is a bit incorrect.
I'm going to remove the vlv mention that inc
On Fri, May 31, 2013 at 08:39:32PM +0100, Chris Wilson wrote:
> On Fri, May 31, 2013 at 11:45:29AM -0700, Ben Widawsky wrote:
> > This is the only place I could find where we don't already unbind the
> > object before freeing it. This change will allow us to have a nice
> > assertion on free about
On Fri, May 31, 2013 at 12:52:03PM -0700, Ben Widawsky wrote:
> On Fri, May 31, 2013 at 08:52:29PM +0200, Daniel Vetter wrote:
> > On Tue, May 28, 2013 at 07:22:34PM -0700, Ben Widawsky wrote:
> > > From: "Xiang, Haihao"
> > >
> > > This will let userland only try to use the new ring
> > > when t
... not the port clock. This allows us to kill the funny semantics
around pixel_target_clock.
Since the dpll code still needs the real port clock, add a new
port_clock field to the pipe configuration. Handling the default case
for that one is a bit tricky, since encoders might not consistently
ove
On Fri, May 31, 2013 at 08:52:29PM +0200, Daniel Vetter wrote:
> On Tue, May 28, 2013 at 07:22:34PM -0700, Ben Widawsky wrote:
> > From: "Xiang, Haihao"
> >
> > This will let userland only try to use the new ring
> > when the appropriate kernel is present
> >
> > Signed-off-by: Xiang, Haihao
>
On Fri, May 31, 2013 at 04:33:24PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> It just prints whether it's supported/enabled/disabled. Feature
> requested by the power management team.
>
> v2: Checkpatch started complaining about seq_printf with 1 argument.
>
> Requested-by: Kristen Acc
On Fri, May 31, 2013 at 11:45:29AM -0700, Ben Widawsky wrote:
> This is the only place I could find where we don't already unbind the
> object before freeing it. This change will allow us to have a nice
> assertion on free about whether or not an object still has pinned pages.
>
> v2: Just use the
From: Paulo Zanoni
It just prints whether it's supported/enabled/disabled. Feature
requested by the power management team.
v2: Checkpatch started complaining about seq_printf with 1 argument.
Requested-by: Kristen Accardi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c |
From: Paulo Zanoni
IPS is still enabled by default. Feature requested by the power
management team.
This should also help testing the feature on some early pre-production
hardware where there were relationship problems between IPS and PSR.
v2: Rebase on top of the newest IPS implementation.
v3:
From: Paulo Zanoni
Intermediate Pixel Storage is a feature that should reduce the number
of times the display engine wakes up memory to read pixels, so it
should allow deeper PC states. IPS can only be enabled on ULT pipe A
with 8:8:8 pipe pixel formats.
With eDP 1920x1080 and correct watermarks
On Fri, May 31, 2013 at 02:24:11PM -0300, Paulo Zanoni wrote:
> 2013/5/31 Daniel Vetter :
> > Now that we track the cpu transcoder we need accurately in the pipe
> > config we can finally fix up the transcoder check. With the current
> > code eDP on port D will be broken since we'd errornously cut
On Fri, May 31, 2013 at 08:09:47PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Loading the palette after the planes are enabled can risk showing
> incorrect colors. ILK+ already load the palette before even the pipe
> is enabled. Just follow the same order for gen2-4 and
On Fri, May 31, 2013 at 7:50 PM, Chris Wilson wrote:
> On Fri, May 31, 2013 at 05:15:10PM +0200, Daniel Vetter wrote:
>> On Fri, May 31, 2013 at 4:05 PM, Paulo Zanoni wrote:
>> > 2013/5/23 Daniel Vetter :
>> >> On Thu, May 23, 2013 at 01:57:17PM +0100, Chris Wilson wrote:
>> >>> If none of the CR
On Tue, May 28, 2013 at 07:22:34PM -0700, Ben Widawsky wrote:
> From: "Xiang, Haihao"
>
> This will let userland only try to use the new ring
> when the appropriate kernel is present
>
> Signed-off-by: Xiang, Haihao
> Reviewed-by: Damien Lespiau
> Signed-off-by: Ben Widawsky
So originally I
On Fri, May 31, 2013 at 11:28:47AM -0700, Ben Widawsky wrote:
> If we properly keep track of the pages_pin_count, then when we later add
> multiple address spaces, the put_pages doesn't need any special checks
> to be able to perform it's job.
>
> CC: Chris Wilson
> Signed-off-by: Ben Widawsky
This is the only place I could find where we don't already unbind the
object before freeing it. This change will allow us to have a nice
assertion on free about whether or not an object still has pinned pages.
v2: Just use the i915 object instead of casting
Signed-off-by: Ben Widawsky
---
drive
On Fri, May 31, 2013 at 11:28:48AM -0700, Ben Widawsky wrote:
> Since it will be used for the global bound/unbound list with full PPGTT,
> this helps clarify things for upcoming code rework.
>
> Recommended-by: Chris Wilson
> Signed-off-by: Ben Widawsky
Reviewed-by: Chris Wilson
-Chris
--
Chr
On Fri, May 31, 2013 at 11:28:45AM -0700, Ben Widawsky wrote:
> It's not terribly interesting to know that a parameter doesn't exist,
> and it can get in the way of interesting messages, especially with the
> staggered VECS merging as we've done.
>
> Signed-off-by: Ben Widawsky
The idiom we have
Since it will be used for the global bound/unbound list with full PPGTT,
this helps clarify things for upcoming code rework.
Recommended-by: Chris Wilson
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c| 11 ++-
drivers/gpu/drm/i915/i915_drv.h| 2 +-
driv
This is the only place I could find where we don't already unbind the
object before freeing it. This change will allow us to have a nice
assertion on free about whether or not an object still has pinned pages.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_fb.c | 1 +
1 file changed,
It's not terribly interesting to know that a parameter doesn't exist,
and it can get in the way of interesting messages, especially with the
staggered VECS merging as we've done.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_dma.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(
If we properly keep track of the pages_pin_count, then when we later add
multiple address spaces, the put_pages doesn't need any special checks
to be able to perform it's job.
CC: Chris Wilson
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 5 +++--
1 file changed, 3 insertion
On Wed, May 29, 2013 at 09:19:25PM +0200, Daniel Vetter wrote:
> On Tue, May 28, 2013 at 07:22:24PM -0700, Ben Widawsky wrote:
> > HSW has some special requirements for the VEBOX. Splitting out the
> > interrupt handler will make the code a bit nicer and less error prone
> > when we begin to handle
On Fri, May 31, 2013 at 05:15:10PM +0200, Daniel Vetter wrote:
> On Fri, May 31, 2013 at 4:05 PM, Paulo Zanoni wrote:
> > 2013/5/23 Daniel Vetter :
> >> On Thu, May 23, 2013 at 01:57:17PM +0100, Chris Wilson wrote:
> >>> If none of the CRTC parameters change along with the framebuffer, we can
> >>
2013/5/31 Daniel Vetter :
> Now that we track the cpu transcoder we need accurately in the pipe
> config we can finally fix up the transcoder check. With the current
> code eDP on port D will be broken since we'd errornously cut the
> power.
>
> For reference see
>
> commit 2124b72e6283c4e84a55e710
On Fri, May 31, 2013 at 05:22:07PM +0200, Daniel Vetter wrote:
> On Fri, May 31, 2013 at 04:11:59PM +0100, Damien Lespiau wrote:
> > On Fri, May 31, 2013 at 09:12:19AM +0200, Daniel Vetter wrote:
> > > This has accidentally been reintroduced with
> > >
> > > commit 22aae764a3fa21ee502b99e8986cb4e4
From: Ville Syrjälä
Loading the palette after the planes are enabled can risk showing
incorrect colors. ILK+ already load the palette before even the pipe
is enabled. Just follow the same order for gen2-4 and VLV.
According to BSpec the requirements for palette access are
display core clock and
From: Ville Syrjälä
There's a bunch of unused members inside drm_plane, bloating the size of
the structure needlessly. Eliminate them.
v2: Remove all of it from kernel-doc too
Reviewed-by: Laurent Pinchart
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_crtc.c | 2 +-
include/drm/drm_c
From: Ville Syrjälä
People don't like typedefs these days. Eliminate their use from intel_fb.c.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_fb.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i9
From: Ville Syrjälä
Use container_of() instead of a cast to get struct intel_fbdev
from struct drm_fb_helper.
Also populate the fb_info->par correctly with the drm_fb_helper pointer
instead of the intel_fbdev pointer.
There's no actual functional change since the drm_fb_helper happens to
be the
From: Ville Syrjälä
Disable sprite planes and cursors when restoring the fbdev mode.
Should makes oopses more readable if they're not covered by sprites and
cursors.
v2: Rebased due to changes earlier in the series
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_fb.c | 23 +++
From: Ville Syrjälä
plane->enabled is never set, so this code didn't do anything.
Fix the code for sprites by calling the new drm_plane_force_disable()
function. That means the plane will remain off until someone explicitly
turns it back on.
And do the same for cursors and the old video overlay
From: Ville Syrjälä
drm_plane_force_disable() will forcibly disable the plane even if user
had previously requested the plane to be enabled.
This can be used to force planes to be off when restoring the fbdev
mode.
The code was simply pulled from drm_framebuffer_remove(), which now
calls the ne
From: Ville Syrjälä
Drivers may need to turn off overlay planes, cursors, etc. when
restoring the fbdev mode. So allow drivers to provide their own
version of drm_fb_helper_restore_fbdev_mode() that can take care
of such details.
Initially just plug in drm_fb_helper_restore_fbdev_mode for all
dr
Another attempt at restoring the fbdev mode.
Changes from v1:
- Cursors and sprites are disabled permanently (well, until someone
explicitly re-enabls them). This was actually already the case for
the old video overlay.
- Since the disabling is now permanent, all extra planes can be
disabled
On Fri, May 31, 2013 at 05:15:10PM +0200, Daniel Vetter wrote:
> On Fri, May 31, 2013 at 4:05 PM, Paulo Zanoni wrote:
> > 2013/5/23 Daniel Vetter :
> >> On Thu, May 23, 2013 at 01:57:17PM +0100, Chris Wilson wrote:
> >>> If none of the CRTC parameters change along with the framebuffer, we can
> >>
On Thu, May 23, 2013 at 06:26:28PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Intermediate Pixel Storage is a feature that should reduce the number
> of times the display engine wakes up memory to read pixels, so it
> should allow deeper PC states. IPS can only be enabled on ULT pipe A
>
On Thu, Apr 18, 2013 at 11:51 PM, Jesse Barnes wrote:
> +static void valleyview_crtc_enable(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
Reviewed-by: Rodrigo Vivi
On Mon, May 13, 2013 at 4:00 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> It just prints whether it's supported/enabled/disabled. Feature
> requested by the power management team.
>
> Requested-by: Kristen Accardi
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gp
Reviewed-by: Rodrigo Vivi
On Thu, May 23, 2013 at 6:26 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Intermediate Pixel Storage is a feature that should reduce the number
> of times the display engine wakes up memory to read pixels, so it
> should allow deeper PC states. IPS can only be enab
Reviewed-by:
Rodrigo Vivi
On Thu, May 16, 2013 at 4:56 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> IPS is still enabled by default. Feature requested by the power
> management team.
>
> This should also help testing the feature on some early pre-production
> hardware where there were relat
On Tue, May 28, 2013 at 09:25:12PM -0300, Rodrigo Vivi wrote:
> WaFbcNukeOn3DBlt for IVB, HSW and VLV.
VLV doesn't have FBC, so this is a bit incorrect.
>
> According BSPec: "Workaround: Do not enable Render Command Streamer tracking
> for FBC.
> Instead insert a LRI to address 0x50380 with dat
Now that we track the cpu transcoder we need accurately in the pipe
config we can finally fix up the transcoder check. With the current
code eDP on port D will be broken since we'd errornously cut the
power.
For reference see
commit 2124b72e6283c4e84a55e71077fee91793f4c801
Author: Paulo Zanoni
D
Now that we track the cpu transcoder we need accurately in the pipe
config we can finally fix up the transcoder check. With the current
code eDP on port D will be broken since we'd errornously cut the
power.
For reference see
commit 2124b72e6283c4e84a55e71077fee91793f4c801
Author: Paulo Zanoni
D
On Fri, May 31, 2013 at 03:53:05PM +0200, Takashi Iwai wrote:
> At Wed, 29 May 2013 19:56:11 +0200,
> Daniel Vetter wrote:
> >
> > Now that we track the cpu transcoder we need accurately in the pipe
> > config we can finally fix up the transcoder check. With the current
> > code eDP on port D will
On Fri, May 31, 2013 at 04:11:59PM +0100, Damien Lespiau wrote:
> On Fri, May 31, 2013 at 09:12:19AM +0200, Daniel Vetter wrote:
> > This has accidentally been reintroduced with
> >
> > commit 22aae764a3fa21ee502b99e8986cb4e49ec14cfe
> > Author: Ben Widawsky
> > Date: Tue May 28 19:22:24 2013
2013/5/31 Daniel Vetter :
> On Fri, May 31, 2013 at 4:05 PM, Paulo Zanoni wrote:
>> 2013/5/23 Daniel Vetter :
>>> On Thu, May 23, 2013 at 01:57:17PM +0100, Chris Wilson wrote:
If none of the CRTC parameters change along with the framebuffer, we can
forgo rewriting the register and waitin
On Fri, May 31, 2013 at 04:44:28PM +0300, Ville Syrjälä wrote:
> On Fri, May 31, 2013 at 10:19:21AM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > Now we compute the results for both 1/2 and 5/6 partitioning and then
> > use hsw_find_best_result to choose which one to use.
> >
> > Wit
On Fri, May 31, 2013 at 09:12:19AM +0200, Daniel Vetter wrote:
> This has accidentally been reintroduced with
>
> commit 22aae764a3fa21ee502b99e8986cb4e49ec14cfe
> Author: Ben Widawsky
> Date: Tue May 28 19:22:24 2013 -0700
>
> drm/i915: Create a more generic pm handler for hsw+
>
> See
2013/5/29 Daniel Vetter :
> Now that we track the cpu transcoder we need accurately in the pipe
> config we can finally fix up the transcoder check. With the current
> code eDP on port D will be broken since we'd errornously cut the
> power.
>
> For reference see
>
> commit 2124b72e6283c4e84a55e710
On Fri, May 31, 2013 at 4:05 PM, Paulo Zanoni wrote:
> 2013/5/23 Daniel Vetter :
>> On Thu, May 23, 2013 at 01:57:17PM +0100, Chris Wilson wrote:
>>> If none of the CRTC parameters change along with the framebuffer, we can
>>> forgo rewriting the register and waiting for a vblank. There are a few
On Fri, May 31, 2013 at 10:08:35AM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We were previously calling sandybridge_update_wm on HSW, but the SNB
> function didn't really match the HSW specification, so we were just
> writing the wrong values.
>
> With this patch, the haswell_update_wm
On Fri, May 31, 2013 at 11:45:06AM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We were previously only setting the WM_PIPE registers, now we are
> setting the LP watermark registers. This should allow deeper PC
> states, resulting in power savings.
>
> We're only using 1/2 data buffer pa
From: Paulo Zanoni
We were previously only setting the WM_PIPE registers, now we are
setting the LP watermark registers. This should allow deeper PC
states, resulting in power savings.
We're only using 1/2 data buffer partitioning for now.
v2: Merge both hsw_compute_pri_wm_* functions (Ville)
v
2013/5/23 Daniel Vetter :
> On Thu, May 23, 2013 at 01:57:17PM +0100, Chris Wilson wrote:
>> If none of the CRTC parameters change along with the framebuffer, we can
>> forgo rewriting the register and waiting for a vblank. There are a few
>> calls made by the display managers as they start up whic
On Fri, May 31, 2013 at 10:12:22AM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We were previously only setting the WM_PIPE registers, now we are
> setting the LP watermark registers. This should allow deeper PC
> states, resulting in power savings.
>
> We're only using 1/2 data buffer pa
At Wed, 29 May 2013 19:56:11 +0200,
Daniel Vetter wrote:
>
> Now that we track the cpu transcoder we need accurately in the pipe
> config we can finally fix up the transcoder check. With the current
> code eDP on port D will be broken since we'd errornously cut the
> power.
>
> For reference see
On Fri, May 31, 2013 at 10:19:21AM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Now we compute the results for both 1/2 and 5/6 partitioning and then
> use hsw_find_best_result to choose which one to use.
>
> With this patch, Haswell watermarks support should be in good shape.
> The only
From: Paulo Zanoni
Now we compute the results for both 1/2 and 5/6 partitioning and then
use hsw_find_best_result to choose which one to use.
With this patch, Haswell watermarks support should be in good shape.
The only improvement we're missing is the case where the primary plane
is disabled: w
From: Paulo Zanoni
We were previously only setting the WM_PIPE registers, now we are
setting the LP watermark registers. This should allow deeper PC
states, resulting in power savings.
We're only using 1/2 data buffer partitioning for now.
v2: Merge both hsw_compute_pri_wm_* functions (Ville)
v
From: Paulo Zanoni
We were previously calling sandybridge_update_wm on HSW, but the SNB
function didn't really match the HSW specification, so we were just
writing the wrong values.
With this patch, the haswell_update_wm function will set the correct
values for the WM_PIPE registers, but it will
Signed-off-by: Imre Deak
---
lib/drmtest.c | 106
lib/drmtest.h | 13 +++
tests/testdisplay.c | 96 ++-
3 files changed, 99 insertions(+), 116 deletions(-)
diff --git a/lib/drmtest.
Add a test going through all connectors/crtcs/modes/formats painting to
a front FB with CPU or painting to a back FB with CPU and blitting it
to the front FB.
Only formats understood by cairo are supported for now.
Signed-off-by: Imre Deak
---
lib/drmtest.c | 101 --
li
These are used by multiple test cases, so make them shared.
Signed-off-by: Imre Deak
---
demos/intel_sprite_on.c | 58 --
lib/drmtest.c | 54 +++
lib/drmtest.h | 3 +++
tests/testdisplay.c
Factor out parts that will be used by an upcoming patch adding
kmstest_create_fb2.
Also call the fb paint functions directly, there is not much
point in passing a function pointer for that.
Signed-off-by: Imre Deak
---
lib/drmtest.c | 176 --
This is used by multiple test cases, so make it shared.
Signed-off-by: Imre Deak
---
lib/drmtest.c | 134
lib/drmtest.h | 14 ++
tests/kms_flip.c| 115
tests/testdisplay.c | 134
On Thu, May 30, 2013 at 04:56:39PM -0700, Ben Widawsky wrote:
> On Wed, May 29, 2013 at 09:43:05PM +0200, Daniel Vetter wrote:
> > This was accidentally broken in the south error interrupt handling
> > work:
> >
> > commit 8664281b64c457705db72fc60143d03827e75ca9
> > Author: Paulo Zanoni
> > Date
This has accidentally been reintroduced with
commit 22aae764a3fa21ee502b99e8986cb4e49ec14cfe
Author: Ben Widawsky
Date: Tue May 28 19:22:24 2013 -0700
drm/i915: Create a more generic pm handler for hsw+
See
commit 58bf8062d0b293b8e1028e5b0342082002886bd4
Author: Daniel Vetter
Date:
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