On Thu, May 30, 2013 at 04:56:39PM -0700, Ben Widawsky wrote: > On Wed, May 29, 2013 at 09:43:05PM +0200, Daniel Vetter wrote: > > This was accidentally broken in the south error interrupt handling > > work: > > > > commit 8664281b64c457705db72fc60143d03827e75ca9 > > Author: Paulo Zanoni <paulo.r.zan...@intel.com> > > Date: Fri Apr 12 17:57:57 2013 -0300 > > > > drm/i915: report Gen5+ CPU and PCH FIFO underruns > > > > Cc: Paulo Zanoni <paulo.r.zan...@intel.com> > > Cc: Ben Widawsky <b...@bwidawsk.net> > > Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch> > Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
Queued for -next, thanks for the review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
