On the series,
Reviewed-by: Jani Nikula
On Tue, 23 Apr 2013, Jesse Barnes wrote:
> On VLV, the Punit doesn't automatically drop the GPU to it's minimum
> voltage level when entering RC6, so we arm a timer to do it for us from
> the RPS interrupt handler. It'll generally only fire when we go i
Context init should have only been called once, ever. The code was
hackish because it predated some of the init cleanups. This patch
refactors the code to leave the part which must be run more than once
(reset, and thaw) as a distinct function.
I need this for some of my future plans to more close
Going forward, every context will have its own address space. So rip off
the band aid now. If contexts fail, don't do ppgtt, and vice versa.
Similarly to the last patch, this is somewhat wasteful of PPGTT address
space with contexts, since we're not actually utilizing the new PPGTT.
Signed-off-by
The aliasing ppgtt is just the ppgtt for the default context.
The obvious downside is until we actually do ppgtt switches, this wastes
a bit of memory. ie. by the end of the series, it's a don't care. The
other downside is PPGTT can't work without contexts, which *should* have
already been the cas
Make resets optional for fini. fini is only ever called in
module_unload. It was therefore a good assumption that the GPU reset
(see the comment in the function) was what we wanted. With an upcoming
patch, we're going to add a few more callsites, one of which is GPU
reset, where doing the extra res
Scary alert.
AFAICT, we simply do not need the guard page if we have the PDEs at the
top since all prefetching is CS related, and it should always be safe to
prefetch into a PDE (provided the PDE is valid). The PDE fetching itself
should not be subject to the prefetching problem, though without fu
The resulting code isn't a huge improvement, but that will change in the
next patch (at least a bit).
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gem.c | 29 ++---
drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +-
From: Chris Wilson
Clients like i915 needs to segregate cache domains within the GTT which
can lead to small amounts of fragmentation. By allocating the uncached
buffers from the bottom and the cacheable buffers from the top, we can
reduce the amount of wasted space and also optimize allocation o
I think this is a nice generalization on it's own, but it's primarily
prep work for my PPGTT support. Does this bother anyone?
The only down side I can see is we waste 2k of cpu unmappable space
(unless we have something else that is <= 2k and doesn't need to be page
aligned).
v2: Align PDEs to 6
It also makes some sense IMO to have these two functions separate
irrespective of the number of callers.
Only the single caller for now, but that will change as we add more
PPGTTs.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 22 +++---
1 file changed, 1
Because our context refcounting doesn't grab a ref at lookup time, it is
unsafe to do so without the lock.
NOTE: We don't have an easy way to put the assertion in the lookup
function which is where this really belongs. Context switching is good
enough because it actually asserts even more correctn
First, I have not finished implementing PPGTT. These are all the patches
I have which I can dump now and not have serious regression risk (and I
think most of them are tolerable on their own). The point is to get
review, make my plans explicit, and get these patches merged.
The main accomplishment
Because PPGTT PDEs within the GTT are calculated in cachelines
(HW guys consistency ftw) we do a divide which will wreak havoc if this
is wrong, and I know that from experience).
If/when we move to multiple PPGTTs this will have to become a WARN, and
return an error. For now however it should alwa
Accomplish this be removing the PDE count define which is (and has
always been) part of the PPGTT structure anyway. With the addition of
the gen specific init function, we can nicely tuck away the magic number
in there.
In this vain, make the PTE define less of a magic number.
The remaining code
This reverts commit fec46b5eff854df5647a9f4724e45dd33933855a.
The latest version of our PM programming doc (which is WAY better than
previous versions, and thanks for that) says something along the lines
of, "On Haswell overclocking is no long achieved via mailbox registers."
Which I misinterprete
From: Zou Nanhai
Needed on SNB to avoid some RC6 related hangs.
v2: remove unneeded defines (Ken)
v3: update to agp-less driver (Jesse)
fixup for new GEM APIs (Jesse)
make debugfs use new locking (Jesse)
Signed-off-by: Zou Nanhai
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/M
The current code is rather ... ugly. The only thing it managed to pull
off is getting 6bpc on DP working on g4x. Then someone added another
custom hack for 6bpc eDP on vlv. Fix up this entire mess by properly
implementing the PIPECONF-based dither/bpc controls on g4x/vlv.
Note that compared to pch
On Tue, Apr 23, 2013 at 10:39:35PM +0200, Daniel Vetter wrote:
> On Tue, Apr 23, 2013 at 06:27:54PM +0300, Ville Syrjälä wrote:
> > The g4x docs are a bit confusing though. They seem to indicate the the
> > PIPECONF dither controls only affect DP.
>
> Hm, this could put a pending question from Jes
On Tue, Apr 23, 2013 at 06:27:54PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 19, 2013 at 08:17:10PM +0200, Daniel Vetter wrote:
> > The current code is rather ... ugly. The only thing it managed to pull
> > off is getting 6bpc on DP working on g4x. Then someone added another
> > custom hack for 6bp
On Mon, 22 Apr 2013 17:23:50 +0300
ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The BIOS uses power of two values for the data/link N value.
>
> Follow suit to make the Zotac DP to dual-HDMI dongle work.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402
> Signe
Thanks Matt.
Reviewers and Daniel, please consider "[PATCH] drm/i915: Add support for
FBC on Ivybridge"
instead of this one.
On Tue, Apr 23, 2013 at 4:04 PM, Matt Turner wrote:
> On Tue, Apr 23, 2013 at 10:52 AM, Rodrigo Vivi
> wrote:
> > This patch introduce Frame Buffer Compression (FBC) s
This patch introduce Frame Buffer Compression (FBC) support for IVB,
without enabling it by default.
It adds a new function gen7_enable_fbc to avoid getting
ironlake_enable_fbc messed with many IS_IVYBRIDGE checks.
v2: Fixes from Ville.
* Fix Plane. FBC is tied to primary plane A in HSW
On Tue, Apr 23, 2013 at 10:52 AM, Rodrigo Vivi wrote:
> This patch introduce Frame Buffer Compression (FBC) support for IVB,
> without enabling it by default.
The summary is kind of confusing, since FBC isn't being enabled by default.
Maybe change it to "drm/i915: Add support for FBC on Ivybridg
Display register 46500h bit 23 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
v2: Ville suggested to enable it back when disabling fbc to avoid wasting
power.
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers
Display register 420B0h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i9
This patch introduce Frame Buffer Compression (FBC) support for HSW.
FBC is tied to primary plane A in HSW.
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 +--
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dr
Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_p
Display register 42000h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
i
This patch introduce Frame Buffer Compression (FBC) support for IVB,
without enabling it by default.
It adds a new function gen7_enable_fbc to avoid getting
ironlake_enable_fbc messed with many IS_IVYBRIDGE checks.
v2: Fixes from Ville.
* Fix Plane. FBC is tied to primary plane A in HSW
Hi all, this series enable Frame Buffer Compression at IVB and HSW.
I decided to create a new function gen7_enable_fbc to avoid getting old
function messed with many IS_IVYBRIDGE and IS_HASWELL checks.
Also I decided to split the needed workarounds in separated patches to be
easy to revert at any
On Tue, 23 Apr 2013 16:28:17 +0300
Ville Syrjälä wrote:
> On Tue, Apr 23, 2013 at 11:45:03AM +0300, Jani Nikula wrote:
> > On Tue, 23 Apr 2013, Jesse Barnes wrote:
> > > On VLV, the Punit doesn't automatically drop the GPU to it's minimum
> > > voltage level when entering RC6, so we arm a timer
Ville noticed this while doing another review; we may as well cancel
this work just to make sure we don't try anything fancy after disabling
the RPS interfaces.
Reported-by: Ville Syrjälä
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c |1 +
1 file changed, 1 insertion(+)
d
We don't want to write reserved regs here, and may want to do other bits
in the future, so split it out.
Reported-by: Ville Syrjälä
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/driv
On VLV, the Punit doesn't automatically drop the GPU to it's minimum
voltage level when entering RC6, so we arm a timer to do it for us from
the RPS interrupt handler. It'll generally only fire when we go idle
(or if for some reason there's a long delay between RPS interrupts), but
won't be re-arm
On Tue, 23 Apr 2013 10:51:28 +0300
Jani Nikula wrote:
> On Tue, 23 Apr 2013, Jesse Barnes wrote:
> > We need to hold the rps lock around punit access.
>
> Reviewed-by: Jani Nikula
>
> And a semi-related question while at it... we will need punit access
> also for non-rps stuff. Shall we just
On Tue, 23 Apr 2013 16:28:17 +0300
Ville Syrjälä wrote:
> On Tue, Apr 23, 2013 at 11:45:03AM +0300, Jani Nikula wrote:
> > On Tue, 23 Apr 2013, Jesse Barnes wrote:
> > > On VLV, the Punit doesn't automatically drop the GPU to it's minimum
> > > voltage level when entering RC6, so we arm a timer
On Tue, Apr 23, 2013 at 10:29:43AM +0300, Jani Nikula wrote:
>
> I think this could be squashed together with the previous patch, but
> either way,
>
> Reviewed-by: Jani Nikula
Entire series merged to dinq, thanks.
-Daniel
>
> On Mon, 22 Apr 2013, Damien Lespiau wrote:
> > Signed-off-by: Dam
On Tue, Apr 23, 2013 at 08:41:10AM -0700, Ben Widawsky wrote:
> Any issue with me pushing the first 2, and stalling on this one?
None at all, the improvements are worthwhile.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mai
On Tue, Apr 23, 2013 at 4:58 PM, Chris Wilson wrote:
> On Tue, Apr 23, 2013 at 04:56:09PM +0200, Daniel Vetter wrote:
>> On Tue, Apr 23, 2013 at 05:27:08PM +0300, Mika Kuoppala wrote:
>> > crtc is holding a reference to a cursor bo and it needs
>> > to be released when crtc is destroyed so that we
On Tue, Apr 23, 2013 at 09:30:33AM +0100, Chris Wilson wrote:
> On Mon, Apr 22, 2013 at 06:11:12PM -0700, Ben Widawsky wrote:
> > This patch is an enormous mess, and I'd be fine if people didn't want
> > it. However I have made the code do what we want at least on the two
> > error dumps I've tried
This way, when adding a device flag we don't have to manually maintain
that list.
v2: undefine the helper macros (Jani Nikula, Daniel Vetter)
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_dma.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
DEV_INFO_FOR_FLAG() now takes 2 parameters:
• A function to apply to the flag
• A separator
This will allow us to use the macro twice in the DRM_DEBUG_DRIVER() call
of i915_dump_device_info().
v2: Fix a typo in the subject (Jani Nikula)
v3: Undef the helper macros (Jani Nikula, Daniel vetter)
On Tue, Apr 23, 2013 at 5:02 PM, Ville Syrjälä
wrote:
> On Fri, Apr 19, 2013 at 11:24:33AM +0200, Daniel Vetter wrote:
>> We need to multiply the hdmi port dotclock by 1.5x since it's not
>> really a dotclock, but the 10/8 encoding bitclock divided by 10.
>>
>> Also add correct limit checks for th
On Fri, Apr 19, 2013 at 08:17:10PM +0200, Daniel Vetter wrote:
> The current code is rather ... ugly. The only thing it managed to pull
> off is getting 6bpc on DP working on g4x. Then someone added another
> custom hack for 6bpc eDP on vlv. Fix up this entire mess by properly
> implementing the PI
On Fri, Apr 19, 2013 at 11:24:36AM +0200, Daniel Vetter wrote:
> They can get at the adjusted mode through intel_crtc->config.
>
> Signed-off-by: Daniel Vetter
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 14 ++
> 1 file changed, 6 insertions(+), 8 del
On Fri, Apr 19, 2013 at 11:24:34AM +0200, Daniel Vetter wrote:
> Prevents black screens when using 30bpp framebuffers on my
> HDMI screens here. The DP input on the same screen though reports a
> 1.4 EDID with the correct 8bpc limit set.
>
> v2: Actually check for the right thing!
>
> Signed-off-
On Fri, Apr 19, 2013 at 11:24:33AM +0200, Daniel Vetter wrote:
> We need to multiply the hdmi port dotclock by 1.5x since it's not
> really a dotclock, but the 10/8 encoding bitclock divided by 10.
>
> Also add correct limit checks for the dotclock and reject modes which
> don't fit. HDMI 1.4 woul
On Tue, Apr 23, 2013 at 04:56:09PM +0200, Daniel Vetter wrote:
> On Tue, Apr 23, 2013 at 05:27:08PM +0300, Mika Kuoppala wrote:
> > crtc is holding a reference to a cursor bo and it needs
> > to be released when crtc is destroyed so that we don't leak
> > the cursor bo.
> >
> > v2: Enhance set and
On Tue, Apr 23, 2013 at 05:27:08PM +0300, Mika Kuoppala wrote:
> crtc is holding a reference to a cursor bo and it needs
> to be released when crtc is destroyed so that we don't leak
> the cursor bo.
>
> v2: Enhance set and move cursor so that disabled
> cursor is handled correctly (Ville Syrjälä)
On Tue, Apr 23, 2013 at 04:28:17PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 23, 2013 at 11:45:03AM +0300, Jani Nikula wrote:
> > On Tue, 23 Apr 2013, Jesse Barnes wrote:
> > > @@ -2895,6 +2913,8 @@ static void valleyview_enable_rps(struct drm_device
> > > *dev)
> > > DRM_DEBUG_DRIVER("setting
crtc is holding a reference to a cursor bo and it needs
to be released when crtc is destroyed so that we don't leak
the cursor bo.
v2: Enhance set and move cursor so that disabled
cursor is handled correctly (Ville Syrjälä)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_display.c |
On Tue, Apr 23, 2013 at 11:45:03AM +0300, Jani Nikula wrote:
> On Tue, 23 Apr 2013, Jesse Barnes wrote:
> > On VLV, the Punit doesn't automatically drop the GPU to it's minimum
> > voltage level when entering RC6, so we arm a timer to do it for us from
> > the RPS interrupt handler. It'll general
On Thu, Apr 11, 2013 at 06:06:23PM +0300, Jani Nikula wrote:
> On Thu, 11 Apr 2013, Egbert Eich wrote:
> > Instead of calling into the DRM helper layer to poll all connectors for
> > changes in connected displays probe only those connectors which have
> > received a hotplug event.
> >
> > Signed-o
From: Ville Syrjälä
The BIOS uses power of two values for the data/link N value.
Follow suit to make the Zotac DP to dual-HDMI dongle work.
v2: Clean up the magic numbers and defines
Change the N clamping to be a bit easier on the eye
Rename intel_reduce_ratio to intel_reduce_m_n_ratio
On Tue, Apr 23, 2013 at 12:13:34PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 22, 2013 at 05:07:23PM +0200, Daniel Vetter wrote:
> > Automatic color range selection was added in
> >
> > commit 55bc60db5988c8366751d3d04dd690698a53412c
> > Author: Ville Syrjälä
> > Date: Thu Jan 17 16:31:29 2013 +
DEV_INFO_FOR_FLAG() now takes 2 parameters:
• A function to apply to the flag
• A separator
This will allow us to use the macro twice in the DRM_DEBUG_DRIVER() call
of i915_dump_device_info().
v2: Fix a typo in the subject (Jani Nikula)
Reviewed-by: Jani Nikula
Signed-off-by: Damien Lespiau
On Tue, Apr 23, 2013 at 10:20:54AM +0300, Jani Nikula wrote:
> On Mon, 22 Apr 2013, Damien Lespiau wrote:
> > DEV_INFO_FOR_FLAG() now takes 2 parameters:
> > • A function to apply to the flag
> > • A separator
>
> Oooh, fancy bullets. ;)
2013 is definitely the year of Unicode!
> Tiny bikesh
On Mon, Apr 22, 2013 at 05:07:23PM +0200, Daniel Vetter wrote:
> Automatic color range selection was added in
>
> commit 55bc60db5988c8366751d3d04dd690698a53412c
> Author: Ville Syrjälä
> Date: Thu Jan 17 16:31:29 2013 +0200
>
> drm/i915: Add "Automatic" mode for the "Broadcast RGB" proper
On Tue, 23 Apr 2013, Jesse Barnes wrote:
> On VLV, the Punit doesn't automatically drop the GPU to it's minimum
> voltage level when entering RC6, so we arm a timer to do it for us from
> the RPS interrupt handler. It'll generally only fire when we go idle
> (or if for some reason there's a long
On Mon, Apr 22, 2013 at 06:11:12PM -0700, Ben Widawsky wrote:
> This patch is an enormous mess, and I'd be fine if people didn't want
> it. However I have made the code do what we want at least on the two
> error dumps I've tried.
>
> The way that it works is it attempts to identify which ACTHD be
On Tue, 23 Apr 2013, Jesse Barnes wrote:
> We need to hold the rps lock around punit access.
Reviewed-by: Jani Nikula
And a semi-related question while at it... we will need punit access
also for non-rps stuff. Shall we just bundle them under the semantically
wrong rps lock? It would also feel
From: "Xiang, Haihao"
Signed-off-by: Xiang, Haihao
Signed-off-by: Zhong Li
---
lib/intel_chipset.h|2 +
tests/Makefile.am |1 +
tests/gem_storedw_loop_vebox.c | 153
3 files changed, 156 insertions(+)
create mode 10064
From: "Xiang, Haihao"
Signed-off-by: Xiang, Haihao
Signed-off-by: Zhong Li
---
tests/gem_ring_sync_loop.c | 37 ++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/tests/gem_ring_sync_loop.c b/tests/gem_ring_sync_loop.c
index b689bcd..2875cf3
On Tue, 23 Apr 2013, Jani Nikula wrote:
> On Mon, 22 Apr 2013, Damien Lespiau wrote:
>> DEV_INFO_FOR_FLAG() now takes 2 parameters:
>> • A function to apply to the flag
>> • A separator
>
> Oooh, fancy bullets. ;)
>
> Tiny bikeshed, is leaving out #undefs for the temp macros intentional?
For
I think this could be squashed together with the previous patch, but
either way,
Reviewed-by: Jani Nikula
On Mon, 22 Apr 2013, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> 2 files changed,
From: "Xiang, Haihao"
The code is surround by a #ifdef...#endif to avoid to break compiling against
the current libdrm release
Signed-off-by: Xiang, Haihao
Signed-off-by: Zhong Li
---
tests/gem_ring_sync_loop.c | 12
1 file changed, 12 insertions(+)
diff --git a/tests/gem_ring
On Mon, 22 Apr 2013, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_
Signed-off-by: Zhong Li
---
tests/gem_ring_sync_loop.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/gem_ring_sync_loop.c b/tests/gem_ring_sync_loop.c
index 955bf34..cb79e7c 100644
--- a/tests/gem_ring_sync_loop.c
+++ b/tests/gem_ring_sync_loop.c
@@ -68,7 +68,
Signed-off-by: Zhong Li
---
tests/gem_non_secure_batch.c |4
1 file changed, 4 insertions(+)
diff --git a/tests/gem_non_secure_batch.c b/tests/gem_non_secure_batch.c
index 5d743c4..bdb3e0b 100644
--- a/tests/gem_non_secure_batch.c
+++ b/tests/gem_non_secure_batch.c
@@ -127,6 +127,10 @@
Signed-off-by: Zhong Li
---
tests/gem_non_secure_batch.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/tests/gem_non_secure_batch.c b/tests/gem_non_secure_batch.c
index 9148b00..5d743c4 100644
--- a/tests/gem_non_secure_batch.c
+++ b/tests/gem_non_
Signed-off-by: Zhong Li
---
tests/gem_exec_nop.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tests/gem_exec_nop.c b/tests/gem_exec_nop.c
index 8608592..d0fa5d5 100644
--- a/tests/gem_exec_nop.c
+++ b/tests/gem_exec_nop.c
@@ -133,7 +133,10 @@ int main(int argc, char
Signed-off-by: Zhong Li
---
tests/gem_cs_tlb.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tests/gem_cs_tlb.c b/tests/gem_cs_tlb.c
index 9f49ac9..6c190d7 100644
--- a/tests/gem_cs_tlb.c
+++ b/tests/gem_cs_tlb.c
@@ -172,7 +172,11 @@ int main(int argc, char **argv)
On Mon, 22 Apr 2013, Damien Lespiau wrote:
> Let's introduce one more of those orthogonal feature macros. This should
> hopefully make the code more readable and make things easier for new platform
> enabling.
>
> This time, HAS_FPGA_DBG_UNCLAIMED() is true for platforms that have bit
> 31 of FPGA
On Mon, 22 Apr 2013, Damien Lespiau wrote:
> DEV_INFO_FOR_FLAG() now takes 2 parameters:
> • A function to apply to the flag
> • A separator
Oooh, fancy bullets. ;)
Tiny bikeshed, is leaving out #undefs for the temp macros intentional?
Reviewed-by: Jani Nikula
>
> This will allow us to us
Add vebox test cases for intel-gfx-tool
Xiang, Haihao (3):
gem_ring_sync_loop: check the rings supported by the kernel
gem_ring_sync_loop: test the new ring
tests: storedw on VEBOX
Zhong Li (5):
gem_cs_tlb.c: add vebox test case
gem_exec_nop.c: add vebox test case
gem_non_secure_batch
On Mon, 22 Apr 2013, Damien Lespiau wrote:
> This way, when adding a device flag we don't have to manually maintain
> that list.
\o/-by: and
Reviewed-by: Jani Nikula
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_dma.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletio
On Mon, 22 Apr 2013, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 31 +++
> 1 file changed, 7 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/d
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