On Fri, Apr 19, 2013 at 11:24:36AM +0200, Daniel Vetter wrote:
> They can get at the adjusted mode through intel_crtc->config.
>
> Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 14 ++++++--------
> 1 file changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 1e6efab..8c36376 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5151,8 +5151,7 @@ static int ironlake_get_refclk(struct drm_crtc *crtc)
> return 120000;
> }
>
> -static void ironlake_set_pipeconf(struct drm_crtc *crtc,
> - struct drm_display_mode *adjusted_mode)
> +static void ironlake_set_pipeconf(struct drm_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -5185,7 +5184,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
> val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>
> val &= ~PIPECONF_INTERLACE_MASK;
> - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> + if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> val |= PIPECONF_INTERLACED_ILK;
> else
> val |= PIPECONF_PROGRESSIVE;
> @@ -5263,8 +5262,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
> }
> }
>
> -static void haswell_set_pipeconf(struct drm_crtc *crtc,
> - struct drm_display_mode *adjusted_mode)
> +static void haswell_set_pipeconf(struct drm_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -5278,7 +5276,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
> val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>
> val &= ~PIPECONF_INTERLACE_MASK_HSW;
> - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> + if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> val |= PIPECONF_INTERLACED_ILK;
> else
> val |= PIPECONF_PROGRESSIVE;
> @@ -5737,7 +5735,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>
> fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
>
> - ironlake_set_pipeconf(crtc, adjusted_mode);
> + ironlake_set_pipeconf(crtc);
>
> /* Set up the display plane register */
> I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
> @@ -5862,7 +5860,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
> if (intel_crtc->config.has_pch_encoder)
> ironlake_fdi_set_m_n(crtc);
>
> - haswell_set_pipeconf(crtc, adjusted_mode);
> + haswell_set_pipeconf(crtc);
>
> intel_set_pipe_csc(crtc);
>
> --
> 1.7.11.7
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
