Is there a planned release date for Main and High profile h.264 encoding
support to be officially released?
Charlie
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On Thu, Mar 07, 2013 at 03:30:25PM +, Damien Lespiau wrote:
> Our static analysis tool noticed that 'reg' could be used uninitialized if
> we are trying to get a PLL to drive VGA and SPLL is already in use
> (plls->spll_refcoung != 0).
>
> In the (error) case above, let's return false to the c
On Thu, Mar 07, 2013 at 03:30:24PM +, Damien Lespiau wrote:
> We weren't initializing wait, which could lead to the use of a random
> value from the stack in the "if (wait)" condition.
>
> Signed-off-by: Damien Lespiau
Reviewed-by: Ben Widawsky
[snip]
--
Ben Widawsky, Intel Open Source Te
On Fri, Mar 08, 2013 at 10:45:52AM -0800, Jesse Barnes wrote:
> The Gunit has a separate reg for this, so allocate some stolen space for
> the power context and initialize the reg.
>
> v2: check for allocation before freeing at cleanup (Jani)
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/
Planes are fixed to pipes in VLV.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f1d6404..5e338c6 100644
---
Port C is for eDP. Port B is shared between HDMI and DP.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3b085bb..3459c64 100644
---
From: Ben Widawsky
Uses slightly different interfaces than other platforms.
v2: track actual set freq, not requested (Rohit)
fix debug prints in init code (Jesse)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_irq.c |5 +-
drivers/g
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07a1333..13bcf8b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/dr
v2: clean up init ordering (Daniel)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_hdmi.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 4d222ec..a285132 100644
--- a/drivers/
From: Pallavi G
Program few Tx buffer Swing control settings through DPIO.
Signed-off-by: Pallavi G
Signed-off-by: Yogesh M
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/intel_display.c |3 +-
drivers/gpu/drm/i915/intel_dp.c | 114 +-
drivers/
We'll re-enable select bits as needed after testing and power measurement.
v2: split out wake handling bits (Jani)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/
Slightly different than other platforms.
v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine.
Signed-off-by: Jesse Barnes
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_reg.h | 22
drivers/gpu/drm/i915/intel_p
From: Pallavi G
For high res modes m n p calculation is fixed for VLV platform.
v2: use 64 bit types and math (Ville)
Signed-off-by: Pallavi G
Signed-off-by: Vijay Purushothaman
Signed-off-by: Yogesh M
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/intel_display.c | 25
We could split this out into a separate routine at some point as an
optimization.
v2: use FORCEWAKE_KERNEL (Ville)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_pm.c | 12 +---
2 files changed, 11 insertions(+), 3 deletions(-)
d
Need to make sure sprites are disabled before shutting off a pipe.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8
The Gunit has a separate reg for this, so allocate some stolen space for
the power context and initialize the reg.
v2: check for allocation before freeing at cleanup (Jani)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h|2 ++
drivers/gpu/drm/i915/i915_gem_stolen.c |
We need to set the 'allow force wake' bit to enable forcewake handling
later on.
v2: split from clock gating patch (Jani)
check for allowwakeack (Ville)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_gem.c |9 +
drivers/gpu/drm/i915/i915_reg.h |2 ++
2 files chang
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1ebed96..af19dca 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@
Can prevent a hang when we get to tessellation. We need to set bit 15
as well for this workaround.
v2: update changelog with accurate info
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Update
vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
appropriate programming.
We need to make sure that the tx lane reset occurs in both the full mode
se
PPS register offsets have changed in Valleyview.
v2: don't clobber port select bits on VLV when fixing up PPS timings
don't bother with G4x PPS regs (Jani)
Signed-off-by: Jesse Barnes
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/g
Needed to handle pre/post enable/disable paths on VLV and avoid a few
fields that are marked reserved on VLV.
v2: don't set color range or DP PLL fields (Jani)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
di
And implement it on ValleyView.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_sprite.c | 11 ++-
include/uapi/drm/i915_drm.h |1 +
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/
No constant alpha yet though, that needs a new ioctl and/or property to
get/set.
v2: use drm_plane_format_cpp (Ville)
fix up vlv_disable_plane, remove IVB bits (Ville)
remove error path rework (Ville)
fix component order confusion (Ville)
clean up platform init (Ville)
use comp
On Fri, 8 Mar 2013 19:06:00 +0200
Ville Syrjälä wrote:
> On Fri, Mar 08, 2013 at 08:52:53AM -0800, Jesse Barnes wrote:
> > On Fri, 08 Mar 2013 15:39:55 +0200
> > Jani Nikula wrote:
> >
> > > On Sat, 02 Mar 2013, Jesse Barnes wrote:
> > > > From: Ben Widawsky
> > > >
> > > > Disable all Gunit
On Fri, Mar 08, 2013 at 08:52:53AM -0800, Jesse Barnes wrote:
> On Fri, 08 Mar 2013 15:39:55 +0200
> Jani Nikula wrote:
>
> > On Sat, 02 Mar 2013, Jesse Barnes wrote:
> > > From: Ben Widawsky
> > >
> > > Disable all Gunit clock gating and make set the "allow force wake" bit.
> > >
> > > Signed-
On Fri, 08 Mar 2013 15:57:19 +0200
Jani Nikula wrote:
>
> I also had this as a quick fix to the backlight access; it's also
> incomplete wrt the backlight registers.
>
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -121,6 +121,9 @@ static int is_backl
On Fri, 08 Mar 2013 15:51:44 +0200
Jani Nikula wrote:
> > + } else {
> > + pp_control_reg = PP_CONTROL;
> > + pp_on_reg = PP_ON_DELAYS;
> > + pp_off_reg = PP_OFF_DELAYS;
> > + pp_div_reg = PP_DIVISOR;
> > + }
>
> Is this else branch needed? ironlake_
On Fri, 08 Mar 2013 15:39:55 +0200
Jani Nikula wrote:
> On Sat, 02 Mar 2013, Jesse Barnes wrote:
> > From: Ben Widawsky
> >
> > Disable all Gunit clock gating and make set the "allow force wake" bit.
> >
> > Signed-off-by: Jesse Barnes
> > ---
> > drivers/gpu/drm/i915/i915_gem.c |4
>
On Fri, 08 Mar 2013 15:33:32 +0200
Jani Nikula wrote:
> > + intel_dpio_write(dev_priv, 0x8438, 0x00760018);
> > + intel_dpio_write(dev_priv, 0x845c, 0x00400888);
> > +
> > + intel_dpio_write(dev_priv, 0x8400, 0x10080);
> > + intel_dpio_write(dev_priv, 0x840
On Wed, 2013-02-06 at 11:10 +, Chris Wilson wrote:
> Read the current hardware state to retrieve the active mode and populate
> our CRTC config if that mode matches our presumptions.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_drv.h |2 +
> drivers/gpu/drm/i91
On Wed, 2013-02-06 at 11:10 +, Chris Wilson wrote:
> Read the current hardware state to retrieve the active mode and populate
> our CRTC config if that mode matches our presumptions.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_drv.h |2 +
> drivers/gpu/drm/i915
On Fri, Mar 08, 2013 at 04:12:23PM +0200, Jani Nikula wrote:
> On Sat, 02 Mar 2013, Jesse Barnes wrote:
> > Fix up a couple of places where we messed with PCH bits on VLV.
>
> I think there's at least a few more spots that need && !IS_VALLEYVIEW():
>
> ---
> } else if (!HAS_PCH_CPT(dev) ||
On the series, excluding the places I commented on,
Acked-by: Jani Nikula
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On Sat, 02 Mar 2013, Jesse Barnes wrote:
> Fix up a couple of places where we messed with PCH bits on VLV.
I think there's at least a few more spots that need && !IS_VALLEYVIEW():
---
} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
if (!HAS_PCH_SPLIT(dev))
I also had this as a quick fix to the backlight access; it's also
incomplete wrt the backlight registers.
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -121,6 +121,9 @@ static int is_backlight_combination_mode(struct drm_device
*dev)
{
struct drm_i
On Sat, 02 Mar 2013, Jesse Barnes wrote:
> PPS register offsets have changed in Valleyview.
>
> Signed-off-by: Jesse Barnes
> Signed-off-by: Gajanan Bhat
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_reg.h |9 ++
> drivers/gpu/dr
On Sat, 02 Mar 2013, Jesse Barnes wrote:
> From: Ben Widawsky
>
> Disable all Gunit clock gating and make set the "allow force wake" bit.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/i915_gem.c |4
> drivers/gpu/drm/i915/i915_reg.h |1 +
> drivers/gpu/drm/i915/intel
On Sat, 02 Mar 2013, Jesse Barnes wrote:
> From: Pallavi G
>
> In Valleyview voltage swing, pre-emphasis and lane control registers can
> be programmed only through the h/w side band fabric. Update
> vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
> appropriate programming.
>
> W
On Wed, 2013-02-06 at 11:10 +, Chris Wilson wrote:
> Signed-off-by: Chris Wilson
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/i915_dma.c |8 +-
> drivers/gpu/drm/i915/i915_drv.h |2 +-
> drivers/gpu/drm/i915/intel_display.c | 14 +-
> drivers/gpu/drm/i915/in
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