I also had this as a quick fix to the backlight access; it's also
incomplete wrt the backlight registers.
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -121,6 +121,9 @@ static int is_backlight_combination_mode(struct drm_device
*dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ if (IS_VALLEYVIEW(dev))
+ return 0;
+
if (INTEL_INFO(dev)->gen >= 4)
return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
@@ -338,12 +341,15 @@ void intel_panel_enable_backlight(struct drm_device *dev,
if (tmp & BLM_PWM_ENABLE)
goto set_level;
- if (dev_priv->num_pipe == 3)
- tmp &= ~BLM_PIPE_SELECT_IVB;
- else
- tmp &= ~BLM_PIPE_SELECT;
+ /* XXX: VLV per pipe registers */
+ if (!IS_VALLEYVIEW(dev)) {
+ if (dev_priv->num_pipe == 3)
+ tmp &= ~BLM_PIPE_SELECT_IVB;
+ else
+ tmp &= ~BLM_PIPE_SELECT;
- tmp |= BLM_PIPE(pipe);
+ tmp |= BLM_PIPE(pipe);
+ }
tmp &= ~BLM_PWM_ENABLE;
I915_WRITE(reg, tmp);
On Sat, 02 Mar 2013, Jesse Barnes <jbar...@virtuousgeek.org> wrote:
> Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 558c6d1..c70e6d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1953,7 +1953,7 @@
> #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
>
> /* Backlight control */
> -#define BLC_PWM_CTL2 0x61250 /* 965+ only */
> +#define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+
> only */
> #define BLM_PWM_ENABLE (1 << 31)
> #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
> #define BLM_PIPE_SELECT (1 << 29)
> @@ -1972,7 +1972,7 @@
> #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
> #define BLM_PHASE_IN_INCR_SHIFT (0)
> #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
> -#define BLC_PWM_CTL 0x61254
> +#define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254)
> /*
> * This is the most significant 15 bits of the number of backlight cycles in
> a
> * complete cycle of the modulated backlight control.
> @@ -1994,7 +1994,7 @@
> #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
> #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
>
> -#define BLC_HIST_CTL 0x61260
> +#define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260)
>
> /* New registers for PCH-split platforms. Safe where new bits show up, the
> * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> @@ -2831,6 +2831,8 @@
> #define DSPFW_HPLL_CURSOR_SHIFT 16
> #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
> #define DSPFW_HPLL_SR_MASK (0x1ff)
> +#define DSPFW4 (dev_priv->info->display_mmio_offset +
> 0x70070)
> +#define DSPFW7 (dev_priv->info->display_mmio_offset +
> 0x7007c)
>
> /* drain latency register values*/
> #define DRAIN_LATENCY_PRECISION_32 32
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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