Re: [Intel-gfx] [PATCH 2/2] drm: Use C8 instead of RGB332 when determining the format from depth/bpp

On Tue, Feb 5, 2013 at 12:55 AM, Daniel Vetter wrote: > On Thu, Jan 31, 2013 at 07:43:38PM +0200, ville.syrj...@linux.intel.com wrote: >> From: Ville Syrjälä >> >> Support for real RGB332 is a rarity, most hardware only really support >> C8. So use C8 instead of RGB332 when determining the format

Re: [Intel-gfx] [PATCH V2 3/3] i915: ignore lid open event when resuming

On Mon, 2013-02-04 at 16:25 +0100, Daniel Vetter wrote: > On Mon, Feb 04, 2013 at 03:10:11PM +0800, Zhang Rui wrote: > > i915 driver needs to do modeset when > > 1. system resumes from sleep > > 2. lid is opened > > > > In PM_SUSPEND_MEM state, all the GPEs are cleared when system resumes, > > thu

[Intel-gfx] [PATCH] Build: Add --disable-tests configure flag to avoid tests build.

Tests are still being built by default. However this request came from OSVs in order to allow them to include i-g-t in their distributions by default avoiding adding more and more dependencies since we are improving and adding more and more tests. Signed-off-by: Rodrigo Vivi --- Makefile.am |

Re: [Intel-gfx] [PATCH 2/2] configure.ac: Do not include `x11-xcb`, `xcb-dri2` and `xcb-aux` in `XVMCLIB`

On Sun, Feb 3, 2013 at 13:29:04 +0100, Paul Menzel wrote: > I was surprised too that no error was generated. Do you have any idea > why compilations succeeds? > Fails to build here with ../../../src/xvmc/intel_xvmc.c:29:25: fatal error: xcb/xcb_aux.h: No such file or directory Also, shared libr

Re: [Intel-gfx] [PATCH xf86-video-intel 1/3] build: Make autoreconf honour ACLOCAL_FLAGS

On Fri, Jan 18, 2013 at 02:13:06PM +, Damien Lespiau wrote: > When running autoreconf, it's possible to give flags to the underlying > aclocal by declaring a ACLOCAL_AMFLAGS variable in the top level > Makefile.am. > > Putting ${ACLOCAL_FLAGS} there allows the user to set an environment > vari

Re: [Intel-gfx] [PATCH 1/3] PM: make VT switching to the suspend console optional v3

On Monday, February 04, 2013 01:37:20 PM Jesse Barnes wrote: > KMS drivers can potentially restore the display configuration without > userspace help. Such drivers can can call a new funciton, > pm_vt_switch_required(false) if they support this feature. In that > case, the PM layer won't VT switc

Re: [Intel-gfx] [PATCH 00/10] [RFC v2] quick dump

On Mon, Feb 04, 2013 at 04:10:55PM +0100, Daniel Vetter wrote: > On Sun, Feb 03, 2013 at 10:13:10AM -0800, Ben Widawsky wrote: > > On Sun, Feb 03, 2013 at 12:22:25PM +, Chris Wilson wrote: > > > On Sun, Feb 03, 2013 at 10:29:15AM +0100, Jesse Barnes wrote: > > > > On Sat, 2 Feb 2013 16:07:52 -

[Intel-gfx] Bug Team Status

Weekly bug team status. This week's team: Imre Deak, Jesse Barnes and Paulo Zanoni. - Pointed some more people at the gpu reset patch for RC6 issues, apparently the people seeing hangs aren't having luck with it. - Work on gathering more documentation to solve some specific bugs - Revisited Haswe

Re: [Intel-gfx] [PATCH] drm/i915: Fix RC6VIDS encode/devoce

On Fri, Feb 01, 2013 at 04:41:14PM -0800, Ben Widawsky wrote: > The RC6 VIDS has a linear ramp starting at 250mv, which means any values > below 250 are invalid. The old buggy macros tried to adjust for this to > be more flexible, but there is no need. As Dan pointed out the ENCODE > only ever has

Re: [Intel-gfx] [PATCH 1/1] tests/gem_ctx_exec: fix destroy ioctl number

On Mon, Feb 04, 2013 at 03:13:30PM +0200, Mika Kuoppala wrote: > Destroy was never called properly > > Signed-off-by: Mika Kuoppala Oops, that's a bit a goof-up, nice catch. While at it, can you please augment the test to check whether a destroyed context doesn't work any more for batchbuffers?

[Intel-gfx] [PATCH 90/90] assembler: Mark format() as PRINTFLIKE in the disassembler

So when making changes in code using that function, we get warnings about mismatches between the format string and arguments. Signed-off-by: Damien Lespiau --- assembler/brw_disasm.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/assembler/brw_disasm.c b/assembler/brw_

[Intel-gfx] [PATCH 89/90] assembler: Fix the decoding of the destination horizontal stride

dest_horizontal_stride needs go through the horiz_stride[] indirection to pick up the rigth stride when its value is 11b (4 elements). Signed-off-by: Damien Lespiau --- assembler/brw_disasm.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/assembler/brw_disasm.c b/ass

[Intel-gfx] [PATCH 88/90] assembler: Group the header inclusions together

Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index 8bfbcfe..dca7f0f 100644 --- a/assembler/gen4asm.h +++ b/assembler/gen4asm.h @@ -34,6 +34,8 @@ #include #include "

[Intel-gfx] [PATCH 86/90] assembler: Remove trailing white space

Signed-off-by: Damien Lespiau --- assembler/brw_eu.c | 16 +++--- assembler/brw_eu_debug.c | 20 +- assembler/brw_eu_emit.c | 48 +++--- assembler/brw_eu_util.c | 18 assembler/disasm-main.c |2 +

[Intel-gfx] [PATCH 85/90] assembler: Use defines for width

Instead of just using hardcoded numbers or resorting to ffs(). Signed-off-by: Damien Lespiau --- assembler/gram.y | 22 +++--- 1 files changed, 11 insertions(+), 11 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index aa6d709..9d58fe6 100644 --- a/assembler/gram

[Intel-gfx] [PATCH 84/90] assembler: Merge declared_register's type into the reg structure

Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |1 - assembler/gram.y| 12 +--- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index 3b98444..49baf9d 100644 --- a/assembler/gen4asm.h +++ b/assembler/gen4asm.h @@ -2

[Intel-gfx] [PATCH 79/90] assembler: Use brw_*() functions for 3-src instructions

Signed-off-by: Damien Lespiau --- assembler/gram.y | 79 +++-- 1 files changed, 28 insertions(+), 51 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index 43c34f6..cd42004 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -108

[Intel-gfx] [PATCH 83/90] assembler: Finish importing brw_eu_*c from mesa

Signed-off-by: Damien Lespiau --- assembler/Makefile.am|2 + assembler/brw_eu_debug.c | 92 ++ assembler/brw_eu_util.c | 125 ++ 3 files changed, 219 insertions(+), 0 deletions(-) create mode 100644 assembler

[Intel-gfx] [PATCH 81/90] assembler: Put struct opcode_desc back in brw_context.h

I originally moved struct opcode_desc from brw_context.h to brw_eu.h on the mesa side, but that was before the realization we needed struct brw_context if we wanted to not touch the code too much. So put it back there now that the mesa patch has been dropped. Signed-off-by: Damien Lespiau --- a

[Intel-gfx] [PATCH 82/90] assembler: Use set_instruction_src1() in send

No reason not to! Signed-off-by: Damien Lespiau --- assembler/gram.y | 17 ++--- 1 files changed, 6 insertions(+), 11 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index cd42004..d69d7b4 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -1200,9 +1200,8 @@ sen

[Intel-gfx] [PATCH 80/90] assembler: Don't pollute the library files with gen4asm.h

gen4asm.h is assembler specific while we want the library files to be somewhat of a proper library. This means that we have to redefine the GL* typedefs for brw_structs.h, not using any of thet GL typedef will be for a future commit. Signed-off-by: Damien Lespiau --- assembler/brw_disasm.c |

[Intel-gfx] [PATCH 78/90] assembler: Add support for D and UD in 3-src instructions

Signed-off-by: Damien Lespiau --- assembler/brw_defines.h |5 + assembler/brw_eu_emit.c | 23 +++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/assembler/brw_defines.h b/assembler/brw_defines.h index 23402e3..98757da 100644 --- a/assembler/brw_defin

[Intel-gfx] [PATCH 77/90] assembler: Expose setters for 3src operands

Signed-off-by: Damien Lespiau --- assembler/brw_eu.h | 17 + assembler/brw_eu_emit.c | 43 +++ 2 files changed, 52 insertions(+), 8 deletions(-) diff --git a/assembler/brw_eu.h b/assembler/brw_eu.h index 6d656a4..20d4b82 100644 ---

[Intel-gfx] [PATCH 76/90] assembler: Introduce set_instruction_saturate()

Also simplify the logic that was setting the saturate bit in the math instruction. Signed-off-by: Damien Lespiau --- assembler/gram.y | 26 ++ 1 files changed, 14 insertions(+), 12 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index 917bccf..43c34f6 100

[Intel-gfx] [PATCH 75/90] assembler: Introduce set_intruction_pred_cond()

This allow us to factor out the test that checks if, when using both predicates and conditional modifiers, we are using the same flag register. Also get rid of of a FIXME that we are now dealing with (the warning mentioned above). Signed-off-by: Damien Lespiau --- assembler/gram.y | 88 ++

[Intel-gfx] [PATCH 74/90] assembler: Introduce set_instruction_opcode()

Signed-off-by: Damien Lespiau --- assembler/gram.y | 72 ++ 1 files changed, 40 insertions(+), 32 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index c6ba086..2d72037 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -82

[Intel-gfx] [PATCH 73/90] assembler: Isolate all the options in their own structure

Like with the predicate fields before, there's no need to use the full instruction to collect the list of options. This allows us to decouple the list of options from a specific instruction encoding. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h | 12 + assembler/gram.y|

[Intel-gfx] [PATCH 72/90] assembler: Unify adding options to the header

Right now we have duplicated code for when the option is the last in the list or not. Put that code in a common function. Interestingly it appears that both sides haven't been kept in sync and that EOT and ACCWRCTRL had limitations on where they had to be in the option list. It's fixed now! Signe

[Intel-gfx] [PATCH 71/90] assembler: Gather all predicate data in its own structure

Rather than user a full instruction for that. Also use set_instruction_predicate() for a case that coud not be done like that before the refactoring (because everyone now uses the same instruction structure). Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |7 ++ assembler/gram.y

[Intel-gfx] [PATCH 70/90] assembler: Move struct relocation out of relocatable instructions

Now that all instructions (relocatable or not) are struct brw_program_instructions, this means we can move the relocation specific information out the "relocatable instruction" structure. This will allow us to share the relocation information between different types of instructions. Signed-off-by:

[Intel-gfx] [PATCH 68/90] assembler: Renamed the instruction field to insn

This will be less typing for the refactoring to come (which is use struct brw_program_instruction in gram.y for the type of all the instructions). Signed-off-by: Damien Lespiau --- assembler/disasm-main.c |6 +++--- assembler/gen4asm.h |4 ++-- assembler/gram.y|6 +++---

[Intel-gfx] [PATCH 67/90] assembler: Use brw_set_src1()

Everything is now aligned to be able to use brw_set_src1() in the opcode generation, so use it. Signed-off-by: Damien Lespiau --- assembler/gram.y | 54 +- 1 files changed, 5 insertions(+), 49 deletions(-) diff --git a/assembler/gram.y b/ass

[Intel-gfx] [PATCH 66/90] assembler: Implement register-indirect addressing mode in brw_set_src1()

The assembler allows people to do that and that's something available since Crestline. Signed-off-by: Damien Lespiau --- assembler/brw_eu_emit.c | 39 +++ 1 files changed, 27 insertions(+), 12 deletions(-) diff --git a/assembler/brw_eu_emit.c b/assembler/br

[Intel-gfx] [PATCH 65/90] assembler: Fix ')' placement in condition

A small typo in the condition. Signed-off-by: Damien Lespiau --- assembler/gram.y |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index 4b5c6a3..c86e28f 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -2226,7 +2226,7 @@ accreg

[Intel-gfx] [PATCH 64/90] assembler: Cleanup visibility of a few global variables/functions

Not everything has to be exported out the compilation unit. Do a small cleanup pass. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |2 + assembler/gram.y| 102 --- assembler/main.c| 12 +++--- 3 files changed, 56 insertions(+

[Intel-gfx] [PATCH 63/90] assembler: Port the warning and error reporting to warn()/error()

This way we ensure to have a single place where these are handled. The immediate benefit is that now line numbers are always printed out, which is quite handy. Signed-off-by: Damien Lespiau --- assembler/gram.y | 274 ++ 1 files changed, 113 i

[Intel-gfx] [PATCH 62/90] assembler: Use brw_set_src0()

Unfortunately, it's all a walk in the park. Both, internal code in the assembler and external shaders (libva) generate registers that trigger assertions in brw_eu_emit.c's brw_validate(). To fix all that I took the option to be able to emit warning with the -W flag but still make the assembler gen

[Intel-gfx] [PATCH 61/90] assembler: Add the input filename to the error/warning messages

Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |2 ++ assembler/gram.y|4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index 1e67c1c..9558a29 100644 --- a/assembler/gen4asm.h +++ b/assembler/gen4asm.h @@ -47,6 +47

[Intel-gfx] [PATCH 60/90] assembler: Add a check for when ExecSize and width are 1

Another check (that we hit if we try to use brw_set_src0()). Again, protect it with the -W option. Signed-off-by: Damien Lespiau --- assembler/gram.y | 26 +- 1 files changed, 25 insertions(+), 1 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index 96bc7

[Intel-gfx] [PATCH 59/90] assembler: Add a check for when width is 1 and hstride is not 0

The list of region restrictions in bspec do say that we can't have: width == 1 && hstrize != 0 We do have plenty of assembly code that don't respect that behaviour. So let's hide the warning under a -W flag (for now) while we fix things. Signed-off-by: Damien Lespiau --- assembler/gen4asm.

[Intel-gfx] [PATCH 58/90] assembler: Add error() and warn() shorthands and use them in set_src[01]

Now that we have locations, we can write error() and warn() functions giving more information about where it's going wrong. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |2 + assembler/gram.y| 121 ++- 2 files changed, 83 insertio

[Intel-gfx] [PATCH 57/90] assembler: Add location support

Let's generate location information about the tokens we are parsing. This can be used to give accurate location when reporting errors and warnings. Signed-off-by: Damien Lespiau --- assembler/gram.y |1 + assembler/lex.l | 24 ++-- 2 files changed, 19 insertions(+), 6

[Intel-gfx] [PATCH 56/90] assembler: Don't warn if identical declared registers are redefined

There's no real need to warn when the same register is declared twice. Currently the libva driver does do that and this warning makes other errors really hide in a sea of warnings. Redefining a register with different parameters is a real error though, so we should not allow that and error out in

[Intel-gfx] [PATCH 55/90] assembler: Store immediate values in reg.dw1.ud

Another step in pushing the parsing in struct brw_reg. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |2 +- assembler/gram.y| 20 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index 0e3b965..58cf1

[Intel-gfx] [PATCH 54/90] assembler: Fix comparisons between reg.type and Architecture registers

Of course the assertion is there to make sure GRF and MRF have a reg.nr < 128. To exclude ARF registers, reg.file has be checked, not reg.type (channel type). Most likely a typo never caught. Signed-off-by: Damien Lespiau --- assembler/brw_eu_emit.c |4 ++-- 1 files changed, 2 insertions(+),

[Intel-gfx] [PATCH 53/90] assembler: ExecSize can be as big as 32 channels

See the IVB PRM, vol4 part3 5.2.3. Signed-off-by: Damien Lespiau --- assembler/brw_eu_emit.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/assembler/brw_eu_emit.c b/assembler/brw_eu_emit.c index ea4baeb..ed24e48 100644 --- a/assembler/brw_eu_emit.c +++ b/assembler/brw

[Intel-gfx] [PATCH 52/90] assembler: Factor out the source register validation

The goal is to use brw_set_src[01](), so let's start by validating the register we have before generating the opcode. Signed-off-by: Damien Lespiau --- assembler/gram.y | 61 ++--- 1 files changed, 25 insertions(+), 36 deletions(-) diff --git a/

[Intel-gfx] [PATCH 51/90] assembler: Use brw_set_dest() to encode the destination

A few notes: I needed to introduce a brw context and compile structs. These are only used to get which generation we are compiling code for, but eventually we can use more of the infrastructure. brw_set_dest() uses the destination register width to program the instruction execution size. The ass

[Intel-gfx] [PATCH 50/90] assembler: Factor out the destination register validation

The goal is to use brw_set_dest(), so let's start by validating the register we have before generating the opcode. Signed-off-by: Damien Lespiau --- assembler/gram.y | 31 +++ 1 files changed, 19 insertions(+), 12 deletions(-) diff --git a/assembler/gram.y b/assemb

[Intel-gfx] [PATCH 49/90] assembler: Use brw_reg in the source operand

Last refactoring step in transition to struct brw_reg. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h | 14 +-- assembler/gram.y| 532 ++- 2 files changed, 269 insertions(+), 277 deletions(-) diff --git a/assembler/gen4asm.h b/assemb

[Intel-gfx] [PATCH 48/90] assembler: Get rid of src operand's swizzle_set

swizzle_set can be derived from the value of swizzle itself, no need for that field. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |1 - assembler/gram.y| 14 -- 2 files changed, 4 insertions(+), 11 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.

[Intel-gfx] [PATCH 47/90] assembler: Consolidate the swizzling configuration on 8 bits

Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |2 +- assembler/gram.y| 67 +- 2 files changed, 24 insertions(+), 45 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index fe09d52..0048b4a 100644 --- a/assembler/

[Intel-gfx] [PATCH 46/90] assembler: Replace struct dst_operand by struct brw_reg

One more step on the road to replacing all register-like structures by struct brw_reg. Two things in this commit are worth noting: * As we are using more and more brw_reg, a lot of the field-by-field assignments can be replaced by 1 assignment which results is a reduction of code * As the de

[Intel-gfx] [PATCH 45/90] assembler: Unify the direct and indirect register type

They are all struct brw_reg registers now. Signed-off-by: Damien Lespiau --- assembler/gram.y | 19 +-- 1 files changed, 9 insertions(+), 10 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index 169026c..e015e0a 100644 --- a/assembler/gram.y +++ b/assembler/gram.

[Intel-gfx] [PATCH 44/90] assembler: Replace struct indirect_reg by struct brw_reg

More code simplification can be layered on top of that (by using some brw_* helpers to create registers), that'd be for another commit. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |8 assembler/gram.y| 46 +++--- 2 files change

[Intel-gfx] [PATCH 43/90] assembler: Replace struct direct_reg by struct brw_reg

More code simplification can be layered on top of that (by using some brw_* helpers to create registers), that'd be for another commit. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |8 -- assembler/gram.y| 202 +- 2 files changed,

[Intel-gfx] [PATCH 42/90] assembler: Make struct declared_register use struct brw_reg

It's time to start converting the emission code in gram.y to use libbrw infrastructure. Let's start with using brw_reg for declared register. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |4 +++- assembler/gram.y| 46 +++--- 2 files chan

[Intel-gfx] [PATCH 41/90] assembler: Don't expose functions only used in main.c

and make then static. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |2 -- assembler/main.c|4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index 388cc75..8dd08b7 100644 --- a/assembler/gen4asm.h +++ b/assembler

[Intel-gfx] [PATCH 40/90] assembler: Make sure nobody adds a field back to struct brw_instruction

Adding something there will break the library, so we might as check for it. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index aeb2b9c..388cc75 100644 --- a/assembl

[Intel-gfx] [PATCH 39/90] assembler: Don't change the size of opcodes!

Until now, the assembler had relocation-related fields added to struct brw_instruction. This changes the size of the structure and break code assuming the opcode structure is really 16 bytes, for instance the emission code in brw_eu_emit.c. With this commit, we build on the infrastructure that slo

[Intel-gfx] [PATCH 38/90] assembler: Make explicit that labels are part of the instructions list

The output of the parsing is a list of struct brw_program_instruction. These instructions can be either GEN instructions aka struct brw_instruction or labels. To make this more explicit we now have a type to test to determine which instruction we are dealing with. This will also allow to to pull t

[Intel-gfx] [PATCH 37/90] assembler: Refactor the code adding instructions and labels

Factoring out the code from the grammar will allow us to switch to using brw_compile in a cleaner way. Signed-off-by: Damien Lespiau --- assembler/gram.y | 84 - 1 files changed, 44 insertions(+), 40 deletions(-) diff --git a/assembler/gram.

[Intel-gfx] [PATCH 36/90] assembler: Make print_instruction() take an instruction

No need to use a brw_program_instruction there as a brw_instruction is what you really dump anyway, espcially when the plan is to use brw_compile from Mesa sooner rather than later. Signed-off-by: Damien Lespiau --- assembler/main.c | 44 ++-- 1 files ch

[Intel-gfx] [PATCH 35/90] assembler: Simplify get_subreg_address()

This function can only be called to resolve subreg_nr in direct mode (there is an other function for the indirect case) and it makes no sense to call it with an immediate operand. Express those facts with asserts and simplify the logic. Signed-off-by: Damien Lespiau --- assembler/gram.y | 17

[Intel-gfx] [PATCH 34/90] assembler: Use subreg_nr to store the address register subreg

Another step towards using struct brw_reg for source and destination operands. Instead of having a separate field to store the sub register number of the address register in indirect access mode, we can reuse the subreg_nr field that was only used for direct access so far. Signed-off-by: Damien L

[Intel-gfx] [PATCH 33/90] assembler: Remove the writemask_set field of struct dest_operand

writemask_set gets in the way of switching to using struct brw_reg and it's possible to derive it from the writemask value. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |1 - assembler/gram.y| 10 -- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/assemb

[Intel-gfx] [PATCH 32/90] assembler: Use BRW_WRITEMASK_XYZW instead of the 0xf constant

Signed-off-by: Damien Lespiau --- assembler/gram.y |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index 55708ca..a27375b 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -32,6 +32,7 @@ #include #include "gen4asm.h" #in

[Intel-gfx] [PATCH 30/90] assembler: Don't use -Wpointer-arith

Mesa's code uses the GNU C extension that allows additions and soustractions on void* (+/- 1). Signed-off-by: Damien Lespiau --- configure.ac |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/configure.ac b/configure.ac index 832c6e4..cd1c201 100644 --- a/configure.ac +++

[Intel-gfx] [PATCH 29/90] assembler: Import brw_eu.c

Another step the road of importing Mesa's emission code. Signed-off-by: Damien Lespiau --- assembler/Makefile.am |1 + assembler/brw_eu.c| 269 + 2 files changed, 270 insertions(+), 0 deletions(-) create mode 100644 assembler/brw_eu.c di

[Intel-gfx] [PATCH 28/90] assembler: Import brw_eu_compact.c

To be able to import brw_eu.c and brw_eu_emit.c later on. This could be used to get the assembler generate compact instructions at some point. Signed-off-by: Damien Lespiau --- assembler/Makefile.am | 23 +- assembler/brw_compat.h |2 + assembler/brw_context.h|4 + assembl

[Intel-gfx] [PATCH 18/90] assembler: Adopt enum brw_message_target from mesa

Signed-off-by: Damien Lespiau --- assembler/brw_defines.h | 44 + assembler/disasm.c | 26 +++--- assembler/gram.y| 84 +- 3 files changed, 81 insertions(+), 73 deletions(-) diff --git a/assembler/brw_

[Intel-gfx] [PATCH 27/90] assembler: Protect gen4asm.h from multiple inclusions

Signed-off-by: Damien Lespiau --- assembler/gen4asm.h |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index e47e9e6..71b8a4d 100644 --- a/assembler/gen4asm.h +++ b/assembler/gen4asm.h @@ -26,6 +26,9 @@ * */ +#ifndef __GE

[Intel-gfx] [PATCH 26/90] assembler: Make an libbrw library

With the brw_* files imported from mesa. There are still a few things in that library that needs gen4asm.h, for instance the GLuint and GLint types. The hope is that eventually libbrw can be split out in its own directory and shared. Signed-off-by: Damien Lespiau --- assembler/Makefile.am | 3

[Intel-gfx] [PATCH 25/90] assembler: Introduce struct brw_context

A lot of the mesa code use struct brw_context to get the GPU generation and various information. Let's stub this structure and initialize it ourselves to be able to resuse mesa's code untouched. Signed-off-by: Damien Lespiau --- assembler/Makefile.am |2 + assembler/brw_context.c | 44 ++

[Intel-gfx] [PATCH 24/90] assembler: Remove white space from brw_eu.h

Signed-off-by: Damien Lespiau --- assembler/brw_eu.h | 16 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/assembler/brw_eu.h b/assembler/brw_eu.h index b7009ff..262a40b 100644 --- a/assembler/brw_eu.h +++ b/assembler/brw_eu.h @@ -2,7 +2,7 @@ Copyright (C) Inte

[Intel-gfx] [PATCH 23/90] assembler: Import ralloc from Mesa

This also add a new brw_compat.h that should help maintaining the diff between mesa's version and our as small as possible. Signed-off-by: Damien Lespiau --- assembler/Makefile.am |3 + assembler/brw_compat.h | 64 +++ assembler/ralloc.c | 482

[Intel-gfx] [PATCH 21/90] assembler: Remove trailing white space from brw_defines.h

Signed-off-by: Damien Lespiau --- assembler/brw_defines.h | 296 +++--- 1 files changed, 148 insertions(+), 148 deletions(-) diff --git a/assembler/brw_defines.h b/assembler/brw_defines.h index f0b358e..23402e3 100644 --- a/assembler/brw_defines.h +++ b/a

[Intel-gfx] [PATCH 19/90] assembler: Rename BRW_ACCWRCTRL_ACCWRCTRL

To a more self-describing define. This hopefully will help its inclusion into Mesa. Signed-off-by: Damien Lespiau --- assembler/brw_defines.h |4 ++-- assembler/gram.y|2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/assembler/brw_defines.h b/assembler/brw_def

[Intel-gfx] [PATCH 17/90] assembler: Remove trailing white spaces from brw_structs.h

Signed-off-by: Damien Lespiau --- assembler/brw_structs.h | 488 +++--- 1 files changed, 244 insertions(+), 244 deletions(-) diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h index 218f11e..db7a9be 100644 --- a/assembler/brw_structs.h +++ b/a

[Intel-gfx] [PATCH 16/90] assembler: Adopt brw_structs.h from mesa

Finally merge both brw_structs.h from mesa. One detail has risen in that last commit, the msg_control field of data port message descriptors. Mesa's msg_control field is sometimes split with messages-specific fields where the assembler (at least for recent generations) exposes the full msg_control

[Intel-gfx] [PATCH 14/90] assembler: Rename branch_2_offset to break_cont

Once again, import the equivalent struct from mesa. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h | 16 +--- assembler/main.c|8 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h index

[Intel-gfx] [PATCH 15/90] assembler: Rename bits3.id and bits3.fd

As always, to sync with mesa. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h |4 ++-- assembler/disasm.c |6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h index 2815256..c442f4a 100644 --- a/assembl

[Intel-gfx] [PATCH 13/90] assembler: Rename branch to branch_gen6

The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h | 17 - assembler/main.c|2 +- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/assembler/

[Intel-gfx] [PATCH 12/90] assembler: Rename gen5 DP pixel_scoreboard_clear to last_render_target

The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h |4 ++-- assembler/disasm.c |2 +- assembler/gram.y| 16 3 files changed, 11 insertions(+), 11

[Intel-gfx] [PATCH 10/90] assembler: Rename dp_gen7 to gen7_dp and sync it with Mesa's

The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. I had to drop how mesa splits msg_control as the current assembly language gives access the the whole msg_control field. Recompiling the xorg and the intel driver of libva shaders doesn't show a

[Intel-gfx] [PATCH 11/90] assembler: Remove struct dp_write_gen6 and struct use gen6_dp

We ended up with 2 structures that where exactly the same, so just use one, which happens to be the one Mesa has. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h | 13 - assembler/gram.y| 16 2 files changed, 8 insertions(+), 21 deletions(-) di

[Intel-gfx] [PATCH 09/90] assembler: Rename dp_gen6 to gen6_dp and sync with Mesa's

The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. I had to drop how mesa splits msg_control as the current assembly language gives access the the whole msg_control field. Recompiling the xorg and the intel driver of libva shaders doesn't show a

[Intel-gfx] [PATCH 08/90] assembler: Rename dp_read_gen6 to gen6_dp_sampler_const_cache

The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h | 27 --- assembler/gram.y|6 +++--- 2 files changed, 19 insertions(+), 14 deletions(-) diff --g

[Intel-gfx] [PATCH 07/90] assembler: Rename three_src_gen6 to da3src

Mesa's brw_structs.h has named/renamed this field to da3src. Sync with them. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h |6 +++--- assembler/gram.y| 30 +++--- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/assembler/brw_stru

[Intel-gfx] [PATCH 05/90] build: Add the debugger compilation status to the summary

Signed-off-by: Damien Lespiau --- configure.ac |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/configure.ac b/configure.ac index ff7e779..832c6e4 100644 --- a/configure.ac +++ b/configure.ac @@ -109,6 +109,7 @@ AC_ARG_ENABLE(shader-debugger, AS_HELP_STRING([--enable-

[Intel-gfx] [PATCH 06/90] assembler: Sync brw_instruction's header with mesa's

Two changes there, a field has been renamed and one bit of padding is now used for compressed instructions. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h | 34 +++--- assembler/disasm.c |8 assembler/gram.y| 30 +++

[Intel-gfx] [PATCH 04/90] build: Only build the assembler if flex and bison are found

And start displaying a nice summary of what we are going to compile. Signed-off-by: Damien Lespiau --- Makefile.am |6 +- configure.ac | 15 +++ 2 files changed, 20 insertions(+), 1 deletions(-) diff --git a/Makefile.am b/Makefile.am index a135531..60fc03e 100644 --- a/Ma

[Intel-gfx] [PATCH 02/90] gitignore: Ignore TAGS files

TAGS files are generated with "make tags" to quickly jump through the code. Ignore those by-products of automake/ctags. Signed-off-by: Damien Lespiau --- .gitignore |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/.gitignore b/.gitignore index 611ab06..bfd59dc 100644 ---

[Intel-gfx] [PATCH 03/90] build: Don't use AM_MAINTAINER_MODE

This does not bring us anything these days, not using the macro at all is the same thing as having it always on. See this discussion: https://www.redhat.com/archives/virt-tools-list/2010-October/msg00049.html Signed-off-by: Damien Lespiau --- autogen.sh |2 +- configure.ac |1 - 2 fil

[Intel-gfx] [PATCH 01/90] build: Add CAIRO_FLAGS to the debugger compilation

The library in lib/ exposes in its main header and thus users must be able to include it. --- debugger/Makefile.am |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/debugger/Makefile.am b/debugger/Makefile.am index d76e2ac..f1e49b9 100644 --- a/debugger/Makefile.am +++ b/de

[Intel-gfx] Sync the assembler with Mesa's opcode emission code

Hey, Some time ago, Daniel mentioned merging the assembler into intel-gpu-tools to lower maintenance cost and have more eyes on the code. This series is the aftermath of that with an effort to sync the opcode emission from Mesa with the assembler. It's also available in my fdo i-g-t tree: http:/

Re: [Intel-gfx] [PATCH V2 3/3] i915: ignore lid open event when resuming

On Mon, Feb 04, 2013 at 03:10:11PM +0800, Zhang Rui wrote: > i915 driver needs to do modeset when > 1. system resumes from sleep > 2. lid is opened > > In PM_SUSPEND_MEM state, all the GPEs are cleared when system resumes, > thus it is the i915_resume code does the modeset rather than > intel_lid

Re: [Intel-gfx] [PATCH 00/10] [RFC v2] quick dump

On Sun, Feb 03, 2013 at 10:13:10AM -0800, Ben Widawsky wrote: > On Sun, Feb 03, 2013 at 12:22:25PM +, Chris Wilson wrote: > > On Sun, Feb 03, 2013 at 10:29:15AM +0100, Jesse Barnes wrote: > > > On Sat, 2 Feb 2013 16:07:52 -0800 > > > Ben Widawsky wrote: > > > > > > > This is my second attemp

Re: [Intel-gfx] [PATCH 2/2] drm: Use C8 instead of RGB332 when determining the format from depth/bpp

On Thu, Jan 31, 2013 at 07:43:38PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Support for real RGB332 is a rarity, most hardware only really support > C8. So use C8 instead of RGB332 when determining the format based on > depth/bpp. > > This fixes 8bpp fbcon on i915, s

[Intel-gfx] [RFC] [PATCH 6/7] drm/i915: reference count for i915_hw_contexts

When using i915_hw_context pointer in request struct, we need to use reference counts as context might be released before request processing takes place. v2: track i915_hw_context pointers instead of using ctx_ids (from Chris Wilson) Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i91

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