The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
Signed-off-by: Damien Lespiau <damien.lesp...@intel.com>
---
assembler/brw_structs.h | 17 ++++++++++++-----
assembler/main.c | 2 +-
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h
index 511c326..7b0b0da 100644
--- a/assembler/brw_structs.h
+++ b/assembler/brw_structs.h
@@ -1125,6 +1125,18 @@ struct brw_instruction
GLuint dest_address_mode:1;
} ia16; /* indirect align16 */
+ struct {
+ GLuint dest_reg_file:2;
+ GLuint dest_reg_type:3;
+ GLuint src0_reg_file:2;
+ GLuint src0_reg_type:3;
+ GLuint src1_reg_file:2;
+ GLuint src1_reg_type:3;
+ GLuint pad:1;
+
+ GLint jump_count:16;
+ } branch_gen6;
+
struct
{
GLuint dest_reg_file:1; /* used in Gen6, deleted in Gen7 */
@@ -1144,11 +1156,6 @@ struct brw_instruction
GLuint dest_reg_nr:8;
} da3src;
- struct
- {
- GLuint pad:16;
- GLint JIP:16;
- } branch; /* conditional branch JIP for Gen6 only */
} bits1;
diff --git a/assembler/main.c b/assembler/main.c
index 15ed517..ae271b4 100644
--- a/assembler/main.c
+++ b/assembler/main.c
@@ -448,7 +448,7 @@ int main(int argc, char **argv)
if(opcode == BRW_OPCODE_CALL || opcode == BRW_OPCODE_JMPI)
entry->instruction.bits3.JIP = offset; // for CALL, JMPI
else
- entry->instruction.bits1.branch.JIP = offset; // for
CASE,ELSE,FORK,IF,WHILE
+ entry->instruction.bits1.branch_gen6.jump_count =
offset; // for CASE,ELSE,FORK,IF,WHILE
} else if(IS_GENp(7)) {
int opcode = entry->instruction.header.opcode;
/* Gen7 JMPI Restrictions in bspec:
--
1.7.7.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
