Dear Thomas,
thanks for the iteration.
Am Mittwoch, den 20.06.2012, 20:03 +0200 schrieb Daniel Vetter:
> On Wed, Jun 20, 2012 at 07:41:51PM +0200, Thomas Richter wrote:
> > This patch adds support for the ns2501 DVO, found in some older
Please also use present tense in the commit summary.
> No need to bisect, we've dug out the issue on latest
> drm-intel-next-queued: One of Jesse Barnes' patches that shouldn't have
> affected anything else than unreleased hw blew up snb & ivb. I've updated
> the branch, it should work now.
What should work, VAAPI or the error_state ?
git reset --h
This is an initial implementation of i915 adaptive backlight support.
The intended use for the adaptive backlight is to generate interrupts
whenever the luminance of the screen changes by some thresholds. The
main caveat with that implementation is that those additional
interrupts will wake up the
On SNB and IVB, there's an MSR (also exposed through MCHBAR) we can use
to read out the amount of energy used over time. Expose this in sysfs
to make it easy to do power comparisons with different configurations.
If the platform supports it, the file will show up under the
drm/card0/power subdire
On Wed, 2012-06-20 at 23:15 +0300, Jani Nikula wrote:
> Restrict hsync start, end, hdisplay and htotal to be according to hw
> spec. Through drm_mode_set_crtcinfo(), these will also limit hblank start,
> end.
I'm pretty sure any physical hardware would balk at modes like this.
Virtual framebuffers
On Wed, 20 Jun 2012 22:53:56 +0200
Daniel Vetter wrote:
> On Wed, Jun 20, 2012 at 10:53:13AM -0700, Jesse Barnes wrote:
> > With the code in place, we can bind the driver, should make bisect possible.
> >
> > Signed-off-by: Jesse Barnes
> Queued all three for -next, thanks for the respin.
Cool
On Wed, Jun 20, 2012 at 10:53:13AM -0700, Jesse Barnes wrote:
> With the code in place, we can bind the driver, should make bisect possible.
>
> Signed-off-by: Jesse Barnes
Queued all three for -next, thanks for the respin.
-Daniel
--
Daniel Vetter
Mail: dan...@ffwll.ch
Mobile: +41 (0)79 365 57
On Wed, Jun 20, 2012 at 9:44 PM, Angela wrote:
> I can bisect, where to start ? Which sources/kernel ?
No need to bisect, we've dug out the issue on latest
drm-intel-next-queued: One of Jesse Barnes' patches that shouldn't
have affected anything else than unreleased hw blew up snb & ivb. I've
upd
From: Chris Wilson
This addresses WaPruneModeWithIncorrectHsyncOffset.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=50236
Signed-off-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
Restrict hsync start, end, hdisplay and htotal to be according to hw
spec. Through drm_mode_set_crtcinfo(), these will also limit hblank start,
end.
Signed-off-by: Jani Nikula
---
Let's see if this will be frowned upon... seems better to have these
separate from the follow-up workaround patch,
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Wednesday, 20 June, 2012 21:29
> To: Angela
> Cc: 'Daniel Vetter'; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [Bug 51061] GPU Hang using VAAPI
>
> On Wed, Jun 20, 2012 at 09:21:07PM +0200, An
On Wed, Jun 20, 2012 at 09:21:07PM +0200, Angela wrote:
> > > Updated xorg-edgers, updated kernel (>3.5-rc3), merged
> > > drm-intel-next-queued. "Fixed" the two conflicts, are they OK ?
> > >
> > > No console, X starts in Vesa Mode.
> > >
> > > Added the new kernel dmesg, my "fixed" conflict's and
> > Updated xorg-edgers, updated kernel (>3.5-rc3), merged
> > drm-intel-next-queued. "Fixed" the two conflicts, are they OK ?
> >
> > No console, X starts in Vesa Mode.
> >
> > Added the new kernel dmesg, my "fixed" conflict's and a good kernel
> dmesg.
> >
> > What's next.
>
> Looks like the ker
Hi Dave,
Resend of the pull as request on irc, all the fancy details are below the
cut. Mail is completely unchanged, so it's still babbling about rc2 and
regression that are tracked down by now ;-)
Cheers, Daniel
---
Hi Dave,
rc2 is out the door so I've figured I'll annoy you with the first -n
On Wed, Jun 20, 2012 at 07:34:29PM +0200, Angela wrote:
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > Dunno which kernel the -extra one is built from, but there's a drm-intel-
> > experimental ppa at
> >
> > http://kernel.ubuntu.com/~kernel-ppa/mainline/drm-intel-
On Wed, Jun 20, 2012 at 07:41:51PM +0200, Thomas Richter wrote:
> This patch adds support for the ns2501 DVO, found in some older
> Fujitsu/Siemens Labtops. It is in the state of "works for me".
> Includes now proper DPMS support. Includes switching between
> resolutions - from 640x480 to 1024x768.
With the code in place, we can bind the driver, should make bisect possible.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4cdff38..ad06ea7 100644
-
Enable the on-chip messaging between the display engine and the GT.
v2: use bit definitions for DPFLIPSTAT reg
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |4 ++--
drivers/gpu/drm/i915/intel_pm.c | 13 +
2 files changed, 15 insertions(+), 2 deletions(-)
di
And restructure the IRQ handling a little. We can use pipestat for most
things, and make sure we don't affect pipe events when enabling and
disabling vblank interupts.
We can leave vblank interrupts masked but enabled so we're not dependent
on the first client to toggle the disable timer. We can
This patch adds support for the ns2501 DVO, found in some older
Fujitsu/Siemens Labtops. It is in the state of "works for me".
Includes now proper DPMS support. Includes switching between resolutions
- from 640x480 to 1024x768. Currently assumes that the native display
resolution is 1024x768.
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Dunno which kernel the -extra one is built from, but there's a drm-intel-
> experimental ppa at
>
> http://kernel.ubuntu.com/~kernel-ppa/mainline/drm-intel-experimental/
>
> which is built from the drm-intel-next-queued b
On 06/20/2012 12:59 PM, Daniel Vetter wrote:
> On Wed, Jun 20, 2012 at 5:53 PM, Chris Wilson
> wrote:
>> On Wed, 20 Jun 2012 08:32:59 -0700, Jesse Barnes
>> wrote:
>>> On Wed, 20 Jun 2012 09:38:25 +0200
>>> Daniel Vetter wrote:
And from the bikeshed departement: Can't we just print a runn
On Wed, Jun 20, 2012 at 5:53 PM, Chris Wilson wrote:
> On Wed, 20 Jun 2012 08:32:59 -0700, Jesse Barnes
> wrote:
>> On Wed, 20 Jun 2012 09:38:25 +0200
>> Daniel Vetter wrote:
>> > And from the bikeshed departement: Can't we just print a running number? I
>> > know, substraction is bloody hard,
On Wed, 20 Jun 2012 08:32:59 -0700, Jesse Barnes
wrote:
> On Wed, 20 Jun 2012 09:38:25 +0200
> Daniel Vetter wrote:
> > And from the bikeshed departement: Can't we just print a running number? I
> > know, substraction is bloody hard, but for anything else than total power
> > consumption (e.g. g
On Wed, 20 Jun 2012 14:57:17 +0200
Daniel Vetter wrote:
> On Fri, Jun 15, 2012 at 11:55:19AM -0700, Jesse Barnes wrote:
> > The PTE format is similar to SNB, but we don't support an MLC and don't
> > need chipset flushing.
> >
> > Signed-off-by: Jesse Barnes
>
> I have my questions whether thi
On Wed, 20 Jun 2012 14:50:51 +0200
Daniel Vetter wrote:
> On Fri, Jun 15, 2012 at 11:55:14AM -0700, Jesse Barnes wrote:
> > From: Shobhit Kumar
> >
> > VLV supports two dp panels, there are two set of panel power sequence
> > registers which needed to be programmed based on the configured
> > p
On Wed, 20 Jun 2012 09:38:25 +0200
Daniel Vetter wrote:
> On Wed, Jun 20, 2012 at 09:20:39AM +0300, Jani Nikula wrote:
> > On Tue, 19 Jun 2012, Jesse Barnes wrote:
> > > On SNB and IVB, there's an MSR (also exposed through MCHBAR) we can use
> > > to read out the amount of energy used over time.
On Fri, Jun 15, 2012 at 11:55:26AM -0700, Jesse Barnes wrote:
> With the code in place, we can bind the driver, should make bisect possible.
>
> Signed-off-by: Jesse Barnes
Ok, I've merged most of these patches, safe for the pageflip/irq stuff
(bikesheds dropped in separate mails) and obviously p
On Fri, Jun 15, 2012 at 11:55:24AM -0700, Jesse Barnes wrote:
> Only count interrupts we find came from the GPU.
>
> Signed-off-by: Jesse Barnes
We have this on every generation's irq handler this way. I guess we should
either fix this everywhere or not bother with it. Dropped for now.
-Daniel
On Fri, Jun 15, 2012 at 11:55:21AM -0700, Jesse Barnes wrote:
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_pm.c |7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d0ce2a5..4fa1a78 100644
On Fri, Jun 15, 2012 at 11:55:25AM -0700, Jesse Barnes wrote:
> We can leave vblank interrupts masked but enabled so we're not dependent
> on the first client to toggle the disable timer. We can also mask all
> render based interrupts, since the ring code will handle unmasking them
> for us.
>
>
On Fri, Jun 15, 2012 at 11:55:19AM -0700, Jesse Barnes wrote:
> The PTE format is similar to SNB, but we don't support an MLC and don't
> need chipset flushing.
>
> Signed-off-by: Jesse Barnes
I have my questions whether this is right, given that MLC died for snb &
ivb, that ivb has grown a L3$
On Fri, Jun 15, 2012 at 11:55:14AM -0700, Jesse Barnes wrote:
> From: Shobhit Kumar
>
> VLV supports two dp panels, there are two set of panel power sequence
> registers which needed to be programmed based on the configured
> pipe. This patch add supports for the same
>
> Acked-by: Acked-by: Ben
On Wed, Jun 13, 2012 at 10:05:39PM +0100, Chris Wilson wrote:
> On Wed, 13 Jun 2012 20:45:19 +0200, Daniel Vetter
> wrote:
> > This is just the minimal patch to disable all this code so that we can
> > do decent amounts of QA before we rip it all out.
> >
> > The complicating thing is that we ne
At Wed, 20 Jun 2012 11:36:51 +0200,
Daniel Vetter wrote:
>
> On Wed, Jun 20, 2012 at 11:21:11AM +0200, Takashi Iwai wrote:
> > At Wed, 20 Jun 2012 10:05:12 +0200,
> > Daniel Vetter wrote:
> > >
> > > On Wed, Jun 20, 2012 at 09:17:41AM +0200, Takashi Iwai wrote:
> > > > This patch fixes the proble
On Wed, Jun 20, 2012 at 11:21:11AM +0200, Takashi Iwai wrote:
> At Wed, 20 Jun 2012 10:05:12 +0200,
> Daniel Vetter wrote:
> >
> > On Wed, Jun 20, 2012 at 09:17:41AM +0200, Takashi Iwai wrote:
> > > This patch fixes the problem on some HP desktop machines with eDP
> > > which give blank screens af
On Tue, Jun 19, 2012 at 06:40:00PM +0200, Daniel Vetter wrote:
> It seems to blow up my ilk in all kinds of strange ways. And now that
> we're no longer resetting the entire modeset state, it shouldn't be
> necessary any longer.
>
> This essentially reverts
>
> commit f817586cebf1b946d1f327f9a596
At Wed, 20 Jun 2012 10:05:12 +0200,
Daniel Vetter wrote:
>
> On Wed, Jun 20, 2012 at 09:17:41AM +0200, Takashi Iwai wrote:
> > This patch fixes the problem on some HP desktop machines with eDP
> > which give blank screens after S3 resume.
> >
> > The problem looks like a timing issue. Although B
On Tue, Jun 19, 2012 at 02:50:17PM -0700, Ben Widawsky wrote:
> On Tue, 19 Jun 2012 17:16:01 +0200
> daniel.vet...@ffwll.ch wrote:
>
> > From: Daniel Vetter
> >
> > Otherwise userspace has no way to figure this out.
> >
> > Signed-Off-by: Daniel Vetter
>
> It would probably be ideal to change
On Wed, Jun 20, 2012 at 09:17:41AM +0200, Takashi Iwai wrote:
> This patch fixes the problem on some HP desktop machines with eDP
> which give blank screens after S3 resume.
>
> The problem looks like a timing issue. Although BLC_PWM_CPU_CTL
> register is already restored at the beginning of resu
On Wed, Jun 20, 2012 at 09:20:39AM +0300, Jani Nikula wrote:
> On Tue, 19 Jun 2012, Jesse Barnes wrote:
> > On SNB and IVB, there's an MSR (also exposed through MCHBAR) we can use
> > to read out the amount of energy used over time. Expose this in debugfs
> > to make it easy to do power compariso
On Wed, Jun 20, 2012 at 08:28:31AM +0200, Angela wrote:
> > > Subject: [Bug 51061] GPU Hang using VAAPI
> > >
> > > https://bugs.freedesktop.org/show_bug.cgi?id=51061
> > >
> > > Chris Wilson changed:
> > >
> > >What|Removed |Added
> > >
> --
This patch fixes the problem on some HP desktop machines with eDP
which give blank screens after S3 resume.
The problem looks like a timing issue. Although BLC_PWM_CPU_CTL
register is already restored at the beginning of resume, it doesn't
seem to take effect. Simply re-issuing the register wri
> > Subject: [Bug 51061] GPU Hang using VAAPI
> >
> > https://bugs.freedesktop.org/show_bug.cgi?id=51061
> >
> > Chris Wilson changed:
> >
> >What|Removed |Added
> >
> > St
On Tue, 19 Jun 2012, Jesse Barnes wrote:
> On SNB and IVB, there's an MSR (also exposed through MCHBAR) we can use
> to read out the amount of energy used over time. Expose this in debugfs
> to make it easy to do power comparisons with different configurations.
>
> Signed-off-by: Jesse Barnes
>
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