On Wed, 15 Feb 2012 15:39:14 +1300
Keith Packard wrote:
> <#part sign=pgpmime>
> On Tue, 14 Feb 2012 11:44:48 -0200, Eugeni Dodonov
> wrote:
>
> > - rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
> > - GEN6_RC_CTL_RC6_ENABLE;
> > + rc6_mask = GEN6_RC_CTL_RC6_ENABLE
On Wed, Feb 15, 2012 at 11:10:08PM +, Chris Wilson wrote:
> On Wed, 15 Feb 2012 23:50:23 +0100, Daniel Vetter
> wrote:
> > + /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
> > +* pipe_control writes because the gpu doesn't properly redirect them
> > +* through
On Wed, 15 Feb 2012 23:50:23 +0100, Daniel Vetter
wrote:
> + /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
> + * pipe_control writes because the gpu doesn't properly redirect them
> + * through the ppgtt for non_secure batchbuffers. */
> + if (unlikely(IS_
On Wed, Feb 15, 2012 at 04:04:28PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> The tool allows you to change the panel fitter settings, so you can
> change the size of the screen being displayed on your monitor without
> changing the real pixel size of your desktop. The biggest use case f
On Sanybridge a few MI read/write commands only work when ppgtt is
enabled. Userspace therefore needs to be able to check whether ppgtt
is enabled. For added hilarity, you need to reset the "use global GTT"
bit on snb when ppgtt is enabled, otherwise it won't work. Despite
what bspec says about a
Now that everything is in place, only bind to the global gtt
when actually required. Patch split-up suggested by Chris Wilson.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_ge
PIPE_CONTROL on snb needs global gtt mappings in place to workaround a
hw gotcha. No other commands need such a workaround. Luckily we can
detect a PIPE_CONTROL commands easily because they have a write_domain
= I915_GEM_DOMAIN_INSTRUCTION (and nothing else has that).
v2: Binding the target of suc
And track the existence of such a binding similar to the aliasing
ppgtt case. Speeds up binding/unbinding in the common case where we
only need a ppgtt binding (which is accessed in a cpu coherent fashion
by the gpu) and no gloabl gtt binding (which needs uc writes for the
ptes).
This patch just p
Note that there's a functional change buried in this patch wrt the ilk
dmar workaround: We now only idle the gpu while tearing down the dmar
mappings, not while clearing the gtt. Keeping the current semantics
would have made for some really ugly code and afaik the issue is only
with the dmar unmapp
Hi all,
This patches here make bindings to the global gtt optional and are
hence preparation work for real per-process gtts. They also have the
benefits that we have fewer changes of randomly scribbling over
things.
The funky part here is the snb workaround, but we have a testcase for
that. And t
On Tue, Feb 14, 2012 at 10:09:07PM +0100, Ben Widawsky wrote:
> These patches are a heavily revised version of the patches I wrote over
> a year ago. These patches have passed basic tests on SNB, and IVB, and
> older versions worked on ILK. In theory, context support should work
> all the way back
On Tue, 14 Feb 2012 22:09:07 +0100, Ben Widawsky wrote:
> These patches are a heavily revised version of the patches I wrote over
> a year ago. These patches have passed basic tests on SNB, and IVB, and
> older versions worked on ILK. In theory, context support should work
> all the way back to G
On Tue, 14 Feb 2012 22:09:12 +0100, Ben Widawsky wrote:
> From: Ben Widawsky
>
> Create all the necessary data structures and hooks to support a context
> API for userspace. Also plumb in the calls from the i915 core into the
> context subsystem. There is a new file i915_context.c which will hol
On Tue, 14 Feb 2012 22:09:15 +0100, Ben Widawsky wrote:
> Extend the flag parameter to support the context id (from the create
> IOCTL) so that userspace can associate a context with the batchbuffer.
>
> Signed-off-by: Ben Widawsky
> @@ -1270,6 +1272,14 @@ i915_gem_do_execbuffer(struct drm_devi
On Tue, 14 Feb 2012 22:09:13 +0100, Ben Widawsky wrote:
> This is the HW dependent context switch code.
>
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_drv.h |3 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 117
> +++
> drivers/gpu/dr
On Wed, 15 Feb 2012 11:39:47 -0800
Eric Anholt wrote:
> On Tue, 14 Feb 2012 22:09:11 +0100, Ben Widawsky wrote:
> > From: Ben Widawsky
> >
> > The GPUs can have different default context layouts, and the sizes could
> > vary based on platform or BIOS. In order to back the context object with
>
On Wed, 15 Feb 2012 19:41:49 +
Chris Wilson wrote:
> On Tue, 14 Feb 2012 22:09:16 +0100, Ben Widawsky wrote:
> > From: Ben Widawsky
> >
> > Parameters tell user space if contexts are available.
> >
> > Signed-off-by: Ben Widawsky
> > ---
> > drivers/gpu/drm/i915/i915_dma.c |2 ++
> >
On Wed, 15 Feb 2012 11:55:56 -0800
Eric Anholt wrote:
> On Tue, 14 Feb 2012 22:09:15 +0100, Ben Widawsky wrote:
> > Extend the flag parameter to support the context id (from the create
> > IOCTL) so that userspace can associate a context with the batchbuffer.
> >
> > Signed-off-by: Ben Widawsky
On Tue, 14 Feb 2012 22:09:15 +0100, Ben Widawsky wrote:
> Extend the flag parameter to support the context id (from the create
> IOCTL) so that userspace can associate a context with the batchbuffer.
>
> Signed-off-by: Ben Widawsky
> /** Resets the SO write offset registers for transform feedb
On Tue, 14 Feb 2012 22:09:16 +0100, Ben Widawsky wrote:
> From: Ben Widawsky
>
> Parameters tell user space if contexts are available.
>
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_dma.c |2 ++
> include/drm/i915_drm.h |1 +
> 2 files changed, 3 insertions
On Tue, 14 Feb 2012 22:09:11 +0100, Ben Widawsky wrote:
> From: Ben Widawsky
>
> The GPUs can have different default context layouts, and the sizes could
> vary based on platform or BIOS. In order to back the context object with
> a properly sized BO, we must read this register in order to find
On Tue, 14 Feb 2012 22:09:09 +0100, Ben Widawsky wrote:
> This is needed for an upcoming workaround.
>
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c |4
> drivers/gpu/drm/i915/intel_ringbuffer.h |5 +
> 2 files changed, 9 insertions(+), 0 deletio
<#part sign=pgpmime>
On Tue, 14 Feb 2012 11:44:48 -0200, Eugeni Dodonov
wrote:
> - rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
> - GEN6_RC_CTL_RC6_ENABLE;
> + rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
> + (IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_R
From: Paulo Zanoni
The tool allows you to change the panel fitter settings, so you can
change the size of the screen being displayed on your monitor without
changing the real pixel size of your desktop. The biggest use case for
this tool is to work around overscan done by TVs and some monitors in
From: Paulo Zanoni
Before this patch, handling dump files was wrong:
- when HAS_PCH_SPLIT was specified, intel_reg_dumper segfaulted inside
intel_check_pch()
- the "devid" variable was used but not set
- there was no way to specify the device id of the machine used to
generate the dump file
From: Paulo Zanoni
Signed-off-by: Paulo Zanoni
---
tools/intel_reg_dumper.c | 25 ++---
1 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index 8c07bbb..66470c4 100644
--- a/tools/intel_reg_dumper.c
+++ b/to
From: Paulo Zanoni
Signed-off-by: Paulo Zanoni
---
tools/intel_reg_dumper.c | 65 +++--
1 files changed, 62 insertions(+), 3 deletions(-)
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index be30fa1..8c07bbb 100644
--- a/tools/intel_r
On Thu, Feb 09, 2012 at 10:23:37AM -0800, Keith Packard wrote:
> <#part sign=pgpmime>
> On Thu, 09 Feb 2012 17:33:23 +, Chris Wilson
> wrote:
> >
> > That code already existed in intel_lvds_init():
> > if (HAS_PCH_SPLIT(dev)) {
> > if (I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
> >
On 2/14/12 8:30 PM, Peter Colberg wrote:
The sink status output of the three events is:
# grep -i sink linux-v3.2-rc2-11398-ge57b688+sink-debug-dmesg
[ 49.653726] [drm:intel_dp_commit], Sink status after training: 0
[ 55.296609] [drm:intel_dp_commit], Sink status after training: 0
[ 77.94
On Wed, Feb 15, 2012 at 02:42:42PM +0100, Ben Widawsky wrote:
> Introduced in commits c1cd90ed and d27b1e0e
>
> Cc: Daniel Vetter
> Signed-off-by: Ben Widawsky
This one smells like gcc being stupid - it's in a static function an gcc
sees all the callsites and we only pass in a const ring argume
On Wed, 15 Feb 2012 13:51:15 +
Chris Wilson wrote:
> On Wed, 15 Feb 2012 14:42:43 +0100, Ben Widawsky wrote:
> > Introduced in commit 8461d226 and 8c59967c
>
> I quibble at the word 'fix', since both are merely silencing the
> compiler. :)
> -Chris
>
I think Daniel isn't taking the patche
On Wed, 15 Feb 2012 14:42:43 +0100, Ben Widawsky wrote:
> Introduced in commit 8461d226 and 8c59967c
I quibble at the word 'fix', since both are merely silencing the
compiler. :)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gf
Introduced in commit 8461d226 and 8c59967c
Cc: Daniel Vetter
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2031cc7..3059082 10064
Introduced in commits c1cd90ed and d27b1e0e
Cc: Daniel Vetter
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ae73288..9f
On Wed, Feb 15, 2012 at 11:25:36AM +, Chris Wilson wrote:
> By recording the location of every request in the ringbuffer, we know
> that in order to retire the request the GPU must have finished reading
> it and so the GPU head is now beyond the tail of the request. We can
> therefore provide a
On Wed, Feb 15, 2012 at 05:26:51PM +0800, Kevin Kuei wrote:
> Hello all,
>
> We are planing to use Intel D2700 CPU (Cedar Trail) as the solution of our
> product, but I can NOT find the linux graphic driver.
> I searched it in:
> http://intellinuxgraphics.org/documentation.html
> and the mailling
By recording the location of every request in the ringbuffer, we know
that in order to retire the request the GPU must have finished reading
it and so the GPU head is now beyond the tail of the request. We can
therefore provide a conservative estimate of where the GPU is reading
from in order to av
So that we can tally the request against the command sequence in the
ringbuffer, or merely jump to the interesting locations.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c |5 +++--
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_irq.c |1
Being able to tally the list of outstanding requests with the sequence
of commands in the ringbuffer is often useful evidence with respect to
driver corruption.
Note that since this is the umpteenth per-ring data structure to be added
to the error state, I've coallesced the nearby loops (the ringb
Hello all,
We are planing to use Intel D2700 CPU (Cedar Trail) as the solution of our
product, but I can NOT find the linux graphic driver.
I searched it in:
http://intellinuxgraphics.org/documentation.html
and the mailling list archieve.
Is there anyone can kindly tell me where can I get the dri
On Tue, 14 Feb 2012 18:17:57 -0500
Adam Jackson wrote:
> On 2/14/12 4:09 PM, Ben Widawsky wrote:
>
> > The IOCTLs defined here may also be used with ppgtt (real ppgtt) but the
> > interface may be insufficient for that. The contexts do provide a
> >
>
> A... what?
This was left up to the reade
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