After copy buffer on preGEN6, it is necessary to wait for the blit to
complete before returning data to the user.
This fixes the piglit test: copy_buffer_coherency.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/intel/intel_buffer_objects.c |7 ++-
1 files changed, 6 insertions(+)
Hello,
I have problem with the I2C clock line, on the 9th clock cycle, after the SCL
goes down it automatically goes up after 8us.
I think SCL line should stay low and delay more than 8us, which should be
chan->algo.udelay = 20 or whatever what was set in intel_i2c_create().
In my attached f
Ted Phelps writes:
> Daniel Vetter writes:
> > If it's short (order of a second or less) can you rehang your gpu with
> > kernel log timestamping switched on?
>
> I'm happy to re-hang the GPU with kernel log timestamping enabled, but I
> won't be able to do so until Sunday night.
I still haven't
Hi,
I've laptop with Intel GM45 graphics:
00:02.0 VGA compatible controller: Intel Corporation Mobile 4 Series
Chipset Integrated Graphics Controller (rev 07)
At home I usually connect external DVI monitor to laptop's HDMI output and
use only external display. Unfortunately I can't close laptop