Hello, I have problem with the I2C clock line, on the 9th clock cycle, after the SCL goes down it automatically goes up after 8us.
I think SCL line should stay low and delay more than 8us, which should be chan->algo.udelay = 20 or whatever what was set in intel_i2c_create(). In my attached file this the first part of the EDID read (A1,00,FF,FF,FF,FF,FF,FF,00...) on /dev/i2c-2 SDVO-B (GPIO 0x5020). Regards, Val
<<attachment: Q965_i2c.JPG>>
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