This is known to lock up the GPU even with the workaround in place.
Signed-off-by: Matthias Hopf
---
src/intel_driver.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/intel_driver.c b/src/intel_driver.c
index 926c7e3..be41712 100644
--- a/src/intel_driver.c
++
Open fbc will cause about 1 Watts power increase on ironlake
for bltk-office/player benchmark. So just disable it and left
code here to waiting for better solution.
Signed-off-by: Alex Shi
---
drivers/gpu/drm/i915/i915_drv.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --
On Thu, 18 Nov 2010 14:53:24 +, Chris Wilson
wrote:
> Eric, only 3 patches (1, 5, 6) turned up in my inbox, can you either resend
> these to me or push to your tree?
Sorry the formatting of the mails produced was confusing. The others
were the DP fixes and the comment fix sent in separate t
Eric, only 3 patches (1, 5, 6) turned up in my inbox, can you either resend
these to me or push to your tree?
Thanks,
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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On Thu, 18 Nov 2010 11:47:12 +0800, Keith Packard wrote:
>
> We were reading our 64-bit value in I915_READ64 and returning 32 bits
> of it. The restoration of fence regs at resume then had a zero end
> value, and the fence had no effect.
>
> Version 2: Split register access functions into per-s
On Thu, 18 Nov 2010 09:32:58 +0800, Eric Anholt wrote:
> The pipe is always set to 8BPC, but here we were leaving whatever
> previous bits were set by the BIOS in place.
This series has now been tested on a DP system. We got flashing garbage
due to the BIOS having configured 6BPC, until this pat
