We need to make sure the eDP PLL is enabled before the pipes or planes,
so do it as part of the DP prepare mode set function.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 39 +
drivers/gpu/drm/i915/intel_dp.c | 63 +++
Useful for capturing register read/write traces to send to the hw guys.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 30 --
1 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i9
We need to use I/O port instructions to access VGA registers on
Ironlake+, and it doesn't hurt on other platforms, so switch the VGA
plane disable function over to using them. Move it to init time as well
while we're at it, no need to repeatedly disable the VGA plane with
every mode set and DPMS e
We should disable the panel first when shutting down an eDP link. And
when turning one on, the panel needs to be enabled before link training
or eDP I/O won't be enabled.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 15 ---
1 files changed, 8 insertions(+), 7
Ironlake requires that we clear the reset panel bit during power
sequences and restore it afterwards. Uncondtionally add code to do that
since it should be harmless on SNB+.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 17 -
1 files changed, 16 insertions(
A small collection of patches to make eDP mode setting work better,
though still not 100% reliably. Includes a register read/write tracer
so I can more easily collect dumps and send them to the hw guys.
Thanks,
Jesse
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Intel-gf
On Sat, Aug 7, 2010 at 11:31 AM, Brian Hall wrote:
> I have a nice little Atom motherboard, the D510MO, with the integrated
> Pineview graphics (GMA 3150). Everything works fine, but my LCD monitor
> never turns off. "xset dpms force suspend" turns off the screen image, but
> the monitor stays in
