[Intel-gfx] [PATCH v2] drm/i915: Add CxSR support on Pineview DDR3

Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li Cc: Zhao Yakui Signed-off-by: Li Peng --- Rebase the patch aga

Re: [Intel-gfx] [PATCH] drm/i915: Add CxSR support on Pineview DDR3

On Mon, May 17, 2010 at 05:26:38PM +0800, Zhenyu Wang wrote: > On 2010.05.17 22:07:30 +0800, Li Peng wrote: > > Pineview with DDR3 memory has different latencies to enable CxSR. > > This patch updates CxSR latency table to add Pineview DDR3 latency > > configuration. It also adds one flag "is_ddr3"

Re: [Intel-gfx] [PATCH 1/4] introduce intel_ring_buffer structure

>>-Original Message- >>From: Daniel Vetter [mailto:dan...@ffwll.ch] >>Sent: 2010年5月18日 1:43 >>To: Zou, Nanhai >>Cc: Owain Ainsworth; Daniel Vetter; Intel GFX; Anholt, Eric >>Subject: Re: [Intel-gfx] [PATCH 1/4] introduce intel_ring_buffer structure >> >>Hi >> >>On Mon, May 17, 2010 at 09:43

Re: [Intel-gfx] [PATCH] enable multiple ring buffer

On Fri, May 14, 2010 at 09:23:02AM +0800, Zou Nan hai wrote: > enable multiple ring buffer support for G45+ chips. > abstract ring buffer structure, add support for BSD(Bit stream decoder) > BSD is a GPU unit used for H.264/VC1 VLD decoding, > > Signed-off-by: Zou Nan hai > Signed-off-by: Xiang H

Re: [Intel-gfx] [PATCH 1/4] introduce intel_ring_buffer structure

On Mon, May 17, 2010 at 09:59:22AM +0800, Zou, Nanhai wrote: > H.264 HW decoding is a huge amount of work, > I can image much more works needed later. > Gem may need some more changes if we continue to improve H.264 decoding work. > e.g currently we found H.264 decoding used too much GPU memory c

Re: [Intel-gfx] [PATCH 1/4] introduce intel_ring_buffer structure

Hi On Mon, May 17, 2010 at 09:43:02AM +0800, Zou, Nanhai wrote: > You may check how user space works in VAAPI code, if you have an > Ironlake system. > We have install guide at http://intellinuxgraphics.org/h264.html. > We have some customer requests for H.264 decoding, so we point to an >

Re: [Intel-gfx] Query on Intel IGP and audio over displayport

On Mon, May 17, 2010 at 3:16 AM, Zhenyu Wang wrote: > > On 2010.05.15 03:46:35 +0200, Mikael Öhman wrote: > > Hello. > > I was wondering if it was possible to send audio over displayport using a Core > > i5 661 (Clarkdale) IGP. > > I have seen some charts indicating that the hardware actually supp

Re: [Intel-gfx] Intel drivers

Hello! I would like to know if your team is working on adding h.264 hardware decoding support for the Intel GMA 4500MHD graphics card and if yes, when it might be available! Thank you! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://li

[Intel-gfx] Unexpected behaviour of xrandr and the Intel driver on monitor hotplug

Hello, Before I file bugs, I'd like to check that the behaviour I'm seeing is unexpected. In all testing, I'm on an Intel 945 platform, running Fedora 12 for most of the stack (including the kernel), but with recent git master of xserver, xf86-video-intel, libdrm and mesa. In all cases, I'm testi

Re: [Intel-gfx] [PATCH] drm/i915: Add CxSR support on Pineview DDR3

On 2010.05.17 22:07:30 +0800, Li Peng wrote: > Pineview with DDR3 memory has different latencies to enable CxSR. > This patch updates CxSR latency table to add Pineview DDR3 latency > configuration. It also adds one flag "is_ddr3" for checking DDR3 > setting in MCHBAR. > This is not against drm-i

[Intel-gfx] [PATCH] drm/i915: Fail to load driver if KMS request without GEM

The i915's implementation of KMS requires GEM in order to manage the memory and execution domains of the framebuffer and associated resources. By the point at which we detect broken a BIOS and need to disable GEM, we have already registered ourselves as a KMS driver with several subsystems. Rather