>>-----Original Message----- >>From: Daniel Vetter [mailto:dan...@ffwll.ch] >>Sent: 2010年5月18日 1:43 >>To: Zou, Nanhai >>Cc: Owain Ainsworth; Daniel Vetter; Intel GFX; Anholt, Eric >>Subject: Re: [Intel-gfx] [PATCH 1/4] introduce intel_ring_buffer structure >> >>Hi >> >>On Mon, May 17, 2010 at 09:43:02AM +0800, Zou, Nanhai wrote: >>> You may check how user space works in VAAPI code, if you have an >>> Ironlake >>system. >>> We have install guide at http://intellinuxgraphics.org/h264.html. >>> We have some customer requests for H.264 decoding, so we point to an >>> early kernel and a similar patch on that page. >> >>I'll try this out. But likely takes a while till I get around - there's >>enough other stuff going on to keep me busy. >> >>> Actually no additional synchronize was add to user space, after BSD >>> decoding is done, we map the BSD output for media pipe input command >>> stream, at this point kernel will wait BSD decoding done before it begin >>> media pipe. >>> >>> so unprivileged client can not damage GPU with this. >>> >>> Though this is not the most efficient way to do the work, >>> >>> One of our optimize plan is to have double ring buffer for H.264 >>> decoding later, e.g. while BSD is decoding to one buffer, media pipe may >>> consume another buffer, >>> >>> So media and BSD ring can work in parallel. Once we begin to do that, we >>> may need to design a better synchronize method. >> >>Well, that's exactly the problem. You simply can't optimize a kernel >>interface once it's in use. And if you try to, your users will get the >>pitchforks and scream bloody murder trying to get you ;) So we need to get >>these patches right (at least the semantics of the interface) beforehand. >> >>> Thanks >>> Zou Nan hai >>
Hi, Since VAAPI will be the only client for this multi ring buffer for a period of time. We may not have so much pain to optimize both kernel and user space. This approach touches little user space interface, only 1 new flag is added to IOCTL. We have new kinds of ring buffer to come in SandyBridge and later chips. Since we are still enabling SandyBridge. I can not for cast how those rings would be synchronized to each other. We may use minimum API to work first. >>Yours, Daniel >>-- >>Daniel Vetter >>Mail: dan...@ffwll.ch >>Mobile: +41 (0)79 365 57 48 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
