On Wed, 2010-04-21 at 23:09 +0800, Adam Jackson wrote:
> On Wed, 2010-04-21 at 16:46 +0800, ykzhao wrote:
> > On Sat, 2010-04-10 at 05:14 +0800, Eric Anholt wrote:
> > > As far as I can tell from reading the specs, this patch just completely
> > > breaks TV detect on GM45. And the logic of "set al
Hi all,
as you know some major distributions are going to ship the 2.6.32
kernel for long term releases. On top of this, some distros (like
Debian) have been using the drm tree from 2.6.33 to provide some
improvement.
However, it appears that the next Debian stable is going to have the
2.9.1 inte
Patch attached.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
>From 63dab13a63c57be8a76ac1f01b
On Wed, 2010-04-21 at 11:09 -0400, Adam Jackson wrote:
> But I really don't see how, short of a really really bad hardware bug,
> turning a subsystem _off_ would make that subsystem work.
Not knowing how the HW works, I'm only guessing.. but the Intel driver
is using a polling based method to det
Was better safe than sorry, but it appears these bits aren't necessary.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_gem.c |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 56ff905..5a
Avoid unnecessary PIPE_CONTROL flushing on non-Ironlake platforms where
it shouldn't be needed.
Signed-off-by: Jesse Barnes
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e6a1cc0..56ff905 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i91
This allows us to do less cache flushing on 965+ chipsets.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_gem.c | 25 +
1 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e7f
Since it's supported on 965 and G4x, enable it there as well.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/i915_irq.c | 33 ++---
2 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/
This gives us finer grained cache control, so should be higher performance.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_gem.c | 52 +-
1 files changed, 39 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gp
Since 965, the hardware has supported the PIPE_CONTROL command, which
provides fine grained GPU cache flushing control. On recent chipsets,
this instruction is required for reliable interrupt and sequence number
reporting in the driver.
So add support for this instruction, including workarounds,
This keeps the memory manager from complaining when we take it down.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_dma.c | 14 ++
drivers/gpu/drm/i915/i915_drv.h |3 +++
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c
Recent hardware supports the PIPE_CONTROL command. It seems to be
necessary for stability on Ironlake at least, and should be a
performance win on other platforms. This patchset (tested on Ironlake
only) adds support for the PIPE_CONTROL command and changes GEM to use
it by default.
There's a st
On Wed, 2010-04-21 at 16:46 +0800, ykzhao wrote:
> On Sat, 2010-04-10 at 05:14 +0800, Eric Anholt wrote:
> > As far as I can tell from reading the specs, this patch just completely
> > breaks TV detect on GM45. And the logic of "set all the bits for the
> > register setting we're going to do and t
On Sat, 2010-04-10 at 05:14 +0800, Eric Anholt wrote:
> On Wed, 7 Apr 2010 17:11:19 +0800, Zhenyu Wang
> wrote:
> > From: ykzhao
> >
> > The TV detection logic is not reliable on the Cantiga platform.
> > Sometimes the TV will be misdetected as the following two cases:
> > - TV is misdetected
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