Hi Vad,
learn make utility.
And i want to know more about target modifiers
aside from .PHONY, like this:
.INTERMEDIATE .SECONDARY
Please show me some simple examples of using this targets
Please check out the GNU make manual here:
http://www.gnu.org/software/make/manual
Look in section 1
Vad,
On Mon, Mar 17, 2008 at 3:02 AM, Vad N <[EMAIL PROTECTED]> wrote:
> book: "Managing Projects with GNU make, 3rd Edition" say :
>
> "Prerequisites of this special target are treated as intermediate files
but
> are never automatically deleted. The most common use of .SECONDARY is to
> mark obj
Sorry for the list spam, but I thought people on this list might be
interested in a new book on using the GNU Autotools, called
Autotools: A Practitioner's Guide to Autoconf, Automake and Libtool
You can find it at free software magazine (freesoftwaremagazine.com):
http://www.freesoftwaremagazin
Vad,
On Tue, Mar 25, 2008 at 1:54 AM, Vad N <[EMAIL PROTECTED]> wrote:
> depend : main.c
> $(CC) -M $(CPPFLAGS) $^ > $@
>
> include depend
> --
>
> I type in command line:
>
> >>make -f myMakefile
> cc -M main.c > depend
> make: 'depend' is up to date.
>
> I assumed th
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Vichy,
If this reply is a one-time thing, then you can simply create a new
message with the same subject line, and copy those in the sender list of
the original message, as well as the list itself. Note that the message
id will be different on the rep
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Hongliang,
You have multiple conflicting rules for "all" and "clean". Here's the
right way to do this (untested):
SUBDIRS = gen ora util
.PHONY: all clean
all clean:
for dir in $(SUBDIRS); do \
ars ago to handle this syntax. Could it have
something to do with the fact that some of the syntax you use is GNU
make specific?
John
Paul Smith wrote:
> On Tue, 2008-04-29 at 08:57 -0600, John Calcote wrote:
>
>> You have multiple conflicting rules for "all" and "clean&qu
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Rupal,
Once you've compiled C or C++ source files in to object files, the
linker can't really tell the difference between them - they're both
object files. The only differences will (probably) be the export
signatures - that is, C++ symbols will be ex
Alan,
Try adding a backslash after the export QA... statement like this:
test:
export QA_STEP=start; \
touch ${QA_STEP};
make executes each line in a separate shell, so QA_STEP will not be set in
the shell that executes the touch statement unless you execute both commands
in the same state
to the shell by using $() syntax, whereas
shell variables are dereferenced by the shell after it receives the command, by
using the ${} syntax.
John
From: kalyan [mailto:kalyanateja...@gmail.com]
Sent: Thursday, February 26, 2009 8:39 PM
To: John Calcote
Cc: albob; Help-make@gnu.org
t; case 2:
> export QA_STEP=start
>
> test:
> @touch ${QA_STEP}
>
> This case worked perfectly :)
>
> Regards
> Kalyan
>
>
>
>
> On Fri, Feb 27, 2009 at 10:20 PM, John Calcote wrote:
>
>> Kaylan,
>>
>>
>>
>> There ar
Werner,
On 4/5/2009 4:49 AM, Werner LEMBERG wrote:
Doing so works fine, however, make says something like
nothing to be done for `debug'
Currently, I do
.PHONY major
ifneq ($(findstring debug,$(MAKECMDGOALS)),)
...
debug:
@:
endif
I've dealt with large G
Hi Paul,
On 5/22/2009 4:01 PM, Paul Smith wrote:
On Fri, 2009-05-22 at 16:24 -0500, Erik Lotspeich wrote:
I have a question about recursive make. I have the FSF GNU Make book by
Richard Stallman& Roland McGrath (covering Make version 3.77). In this
book, it describes the following as equ
Hi Mike,
This is probably the most thought that's gone into make in 25 years. I'm
sure I'm wrong, actually, since I'm not very familiar with the current
state of the literature, but let me restate to make it an opinoin
instead of a statement:
This is really cool stuff. I'm going to download,
so
I may just take a stab at it.
John
On 6/9/2009 10:37 PM, John Calcote wrote:
Hi Mike,
This is probably the most thought that's gone into make in 25 years.
I'm sure I'm wrong, actually, since I'm not very familiar with the
current state of the literature, but le
Hi Jason,
You can either include one makefile in the other:
---
# Makefile A
...
include directory-b/makefile
...
---
or you can call one makefile from the other:
---
# Makefile A
all: $(deps)
...
cd directory-b && $(MAKE) $(MAKEFLAGS) $@
...
...
-
Hi Eduardo,
On 7/13/2009 8:10 AM, Eduardo Sorribas wrote:
Hello.
I have some time using GNU Make, and It has always been ok to me. It's
just that I want to do something I hadn't needed to do, I need to
compile using a mekefile and another compiler different to GCC. How
can I do that? I know
Hello,
On 7/13/2009 8:51 PM, 雷 高 wrote:
If the target of a rule does not exist or the timestamp of the target
is older than any of the prerequisites, the target is out of date. My
question is that if some files of prerequisites does not exist, how
can we compare the timestamp.
For example:
fo
Hi Leandro,
On 8/12/2009 8:46 AM, Leandro Lucarella wrote:
Hi. I would like to be able to include a generated file each time I run
make. I have a small script that generates some make rules. The file
should be generated *always*, and the results of the file should be
included by make.
I tried s
Hi Pan,
On 8/17/2009 12:22 AM, Pan ruochen wrote:
Hi All,
Here is my Makefile:
PHONY: api FW
all: api FW
api:
@make -C DIR1 -n api
@make -C DIR2 -n api
FW:
@make -C DIR1 -n clean depend all
@make -C DIR2 -n clean depend al
On 8/17/2009 11:34 AM, John Calcote wrote:
Hi Pan,
On 8/17/2009 12:22 AM, Pan ruochen wrote:
Hi All,
Here is my Makefile:
PHONY: api FW
all: api FW
api:
@make -C DIR1 -n api
@make -C DIR2 -n api
FW:
@make -C DIR1 -n clean
On 8/18/2009 9:56 PM, Eric Melski wrote:
Schuster, Peter wrote:
The ideal solution is for make to link all 3 output files together, so
that as soon as it fires the job to process any of the 3, all 3 are
marked as “running” and no further jobs are started. Is this possible
with make?
I recen
On 8/21/2009 9:14 AM, Yuri Shtil wrote:
Philip Guenther wrote:
On Thursday, August 20, 2009, Yuri Shtil wrote:
It look like the shell function is evaluated even though commented
out in the following code:
define FUNC
###FOO := $(shell sleep 10)
endef
all:
@echo DONE
$(eval $(call FUNC,$
On 8/22/2009 5:04 PM, Philip Guenther wrote:
On Sat, Aug 22, 2009 at 2:38 PM, John Calcote wrote:
...
You have to admit that Yuri has a valid point here. 99. percent of all
developers know that a hash mark starts a comment, wherein the following
text is ignored until the next newline
Hi Kevin,
On 8/31/2009 7:09 PM, Kevin wrote:
Hi, all:
I have a question about print the project compile date.
I have a project which contains 2 files: "a.c" and "b.c"*. *I want to
print project compile date in one of these 2 files. I put it in a.c:
>>>
// This is a.c
#inc
On 8/31/2009 10:29 PM, Mike Shal wrote:
On 9/1/09, John Calcote wrote:
Basically, you're telling us that you want a.c to compile every time you
build your project, so that you get the latest date/time stamp from the
latest build. I guess the exception to this might be that you only
On 9/22/2009 10:18 AM, Paul Smith wrote:
So, in your case, running the command "mkdir -p gllib; cd gllib;
make" (which by the way, is not well-formed; it should be:
mkdir -p $@&& cd $@&& $(MAKE)
I'm kinda curious to know what $(MAKE) is expected to do in this case.
You just crea
Hi Paul,
On 9/28/2009 3:22 PM, Paul Smith wrote:
On Mon, 2009-09-28 at 13:50 -0700, Michael Morrell wrote:
I was wide open to ideas on ways people deal with not wanting to
hardcode a list of source filenames in the Makefiles. I thought this
was common enough that perhaps there was a builti
On 10/13/2009 12:41 PM, Denis Onischenko wrote:
.../arch/powerpc/Makefile:168: *** mixed implicit and normal rules. Stop.
The message means that some targets in the target list have '%' (the
pattern character) in them, and some don't. This isn't allowed because
pattern rule commands can
Hi Madhav,
On 10/15/2009 8:03 AM, Madhav Ancha wrote:
Hi,
When I run the linker through the command line like this, it works.
g++ -g -pg -fprofile-arcs -ftest-coverage -Lrelease1 -o testApp
file.o -lSharedLib
But when i run from a make file with the follow equivalent
commands, it
Hi Mark,
On 11/3/2009 1:54 PM, Mark Galeck (CW) wrote:
Hello, I see the following recommendation for a "subsystem" recursive
make in the gnu make manual:
subsystem:
$(MAKE) -C subdir
Well, I must not be understanding something, because this does not
make (no pun) sense to me
On 11/20/2009 4:18 PM, Peng Yu wrote:
On Fri, Nov 20, 2009 at 5:11 PM, David Boyce wrote:
On Fri, Nov 20, 2009 at 5:42 PM, Peng Yu wrote:
Is there way to specify a dependence on a directory?
directory: somefile
some_command
If any file in 'directory' is older than 'somefile', th
Hi Timothy,
On 2/5/2010 8:59 AM, Canham, Timothy K (316C) wrote:
Newbie on the list, so forgive me if this is asked frequently:
We have code generation, and we have a rule like this:
fileout1.txt fileout2.txt fileout3.txt: filein.txt
filegen.sh filein.txt
What you need to realiz
Darn it Eric! I keep forgetting about your site. I'm going to have to
put a yellow sticky note on my computer so I remember to go read this
stuff. These are GREAT articles.
Thanks,
John
On 2/5/2010 9:40 AM, Eric Melski wrote:
Canham, Timothy K (316C) wrote:
We have code generation, and we ha
Hi Steve,
I this what you're talking about:
$ sudo -s
root's password:
# echo $PATH
/usr/sbin:/bin:/usr/bin:/sbin
# make
/usr/sbin:/bin:/usr/bin:/sbin
#
# cat Makefile
all:
@echo $(PATH)
#
# make --version
GNU Make 3.81
Copyright (C) 2006 Free Software Foundation, Inc.
This is free soft
On 3/31/2010 2:27 AM, Payal wrote:
Hi,
all:
cmd1 ; cmd2; cmd3
How to ignore errors from cmd2 only? Putting -cmd2 will not work here.
How about this:
all: c1 c2 c3
c1:
cmd1
c2:
-cmd2
c3:
cmd3
John
___
Help-
On 3/31/2010 9:59 AM, David Boyce wrote:
On Wed, Mar 31, 2010 at 11:37 AM, John Calcote wrote:
How about this:
all: c1 c2 c3
c1:
cmd1
c2:
-cmd2
c3:
cmd3
This would work but would also require:
.PHONY: c1 c2 c3
.NOTPARALLEL:
and is generally less useful
On 3/31/2010 11:05 AM, David Boyce wrote:
On Wed, Mar 31, 2010 at 12:36 PM, John Calcote wrote:
On 3/31/2010 9:59 AM, David Boyce wrote:
On Wed, Mar 31, 2010 at 11:37 AM, John Calcote
wrote:
How about this:
all: c1 c2 c3
c1:
cmd1
c2:
-cmd2
c3
Hi Charles,
I'm sorry you've spent so much time looking for a version of make for
your system. I'm surprised you need to search for it. Most systems come
with a version of make already installed. GNU make is not required to
build the GNU make source distribution - any make will do - even the o
German,
This is easier than you think. Just remove the $(shell ... ) from around
your shell call and add the call to a target like this:
check_code:
/path/to/my/script.sh
Then put the check_code target in your dependency graph somewhere.
Scripts return values to the shell. If you call th
On 8/28/2010 5:42 PM, Paul Smith wrote:
> On Sat, 2010-08-21 at 14:13 +0430, ali hagigat wrote:
>> Each explanation has some components. An explanation is written IF AND
>> ONLY IF its components have been written and explained FIRST.
> If you ever try to write documentation for a complicated soft
Hi Luyang,
It's well understood by the community that example code is one area where
the GNU manuals are lacking. The trouble is that the GNU efforts are mostly
volunteer and the people who contribute barely have enough time to write the
reference material. We thank them for their efforts. Neverth
> But if I remove the following line:
> CPPFLAGS = -I include
> The make file is not working..meaning that this line is needed for finding
header
> files from include directory. Please make me correct if I am missing
something...
> Than why the line "VPATH = src include " is not serving the purpos
> -Original Message-
> From: help-make-bounces+john.calcote=gmail@gnu.org [mailto:help-
> make-bounces+john.calcote=gmail@gnu.org] On Behalf Of Bryan Ischo
> Sent: Sunday, April 01, 2012 5:18 PM
> To: help-make@gnu.org
> Subject: Re: CFLAGS/LDFLAGS for PIE vs PIC?
>
> On 04/01/12 1
Jarod,
You're trying to use make as a procedural language processor. Make is
a declarative language. With procedural languages, you describe tasks
that need to be done and the process for executing those tasks. With
declarative languages, you describe the relationships between input
objects and ou
Use \$.
On Apr 18, 2017 10:14 AM, "Richard Cavell" wrote:
>Hello all. For debugging purposes, I am trying to put this into my
>makefile:
>
>.PHONY: dumpvars
>
>dumpvars: source.c source.h
>@echo "$(RM) is " $(RM)
>@echo "$? expands to : " $?
>
>and so on. But obviou
Actually, use \$$. Double the dollar sign to escape it for make. Prepend
the slash (or put it in single quotes) to keep the shell from expanding it.
On Apr 18, 2017 10:16 AM, "John Calcote" wrote:
> Use \$.
>
> On Apr 18, 2017 10:14 AM, "Richard Cavell" wrote:
>
$ cat Makefile
TARGET := i386-x-openbsd5.5y
iflags := \
case "$(TARGET)" in \
i386-*-openbsd5.[5-9]*|i386-*-openbsd[6-9].*)\
echo "-ccopt -nopie";; \
*);; \
esac
flags := $(shell $(iflags))
all:
echo $(flags)
$ make
echo -ccopt -nopie
-ccopt -nopie
If you can't get
Hi Chris,
Make uses file existence and last-modified timestamps to determine if a
target is newer than it's prerequisites. There are other tools that use
checksums like md5, but make only uses presence and timestamps.
John
On Thu, May 2, 2019 at 11:52 AM wrote:
> Hi all
>
> Say I would like t
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