Actually, use \$$. Double the dollar sign to escape it for make. Prepend the slash (or put it in single quotes) to keep the shell from expanding it.
On Apr 18, 2017 10:16 AM, "John Calcote" <john.calc...@gmail.com> wrote: > Use \$. > > On Apr 18, 2017 10:14 AM, "Richard Cavell" <richardcav...@mail.com> wrote: > >> Hello all. For debugging purposes, I am trying to put this into my >> makefile: >> >> .PHONY: dumpvars >> >> dumpvars: source.c source.h >> @echo "$(RM) is " $(RM) >> @echo "$? expands to : " $? >> >> and so on. But obviously, Make is expanding all instances of the >> variables' names. How do I prevent this? >> >> TIA, >> Richard >> _______________________________________________ >> Help-make mailing list >> Help-make@gnu.org >> https://lists.gnu.org/mailman/listinfo/help-make >> > _______________________________________________ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make
