[gem5-users] Use SE mode to simulate Sparc V8

2021-09-26 Thread yangyuqing--- via gem5-users
The gem5 simulator models a single core of a UltraSPARC T1 processor, it uses Sparc V9. However, I want to simulate processors with Sparc V8. Can someone tell me some easy ways? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an e

[gem5-users] set cache line size under o3 cpu

2021-09-29 Thread yangyuqing--- via gem5-users
When I simulate o3 cpu, I find that I can not set cache line size to 32B. The command is ./build/RISCV/gem5.opt --outdir=output/riscv configs/example/se.py \ --cpu-type=DerivO3CPU --num-cpus=2 --cpu-clock=1.5GHz --caches --l2cache --l1d_size=16kB \ --l1i_size=16kB --l2_size=256kB --l1d_assoc=4 -

[gem5-users] encounter a problem when using O3 CPU under PowerPC ISA

2021-09-29 Thread yangyuqing--- via gem5-users
When I use the following command to simulate, I encounter a problem. ./build/POWER/gem5.opt --outdir=output/powerpc configs/example/se.py \ --cpu-type=DerivO3CPU --num-cpus=1 --cpu-clock=132MHz --caches --l2cache --l1d_size=32kB \ --l1i_size=32kB --l2_size=1MB --l1d_assoc=8 --l1i_assoc=8 --l2_asso

[gem5-users] encounter problems about cache options under SE mode

2020-04-27 Thread yangyuqing--- via gem5-users
I use this command to run gem5 under SE mode. ./build/X86/gem5.opt configs/example/se.py --cpu-type=TimingSimpleCPU --cpu-clock=1GHz --caches --l2cache --l1d_size=64kB --l1i_size=32kB --l2_size=256kB --l1d_assoc=8 --l1i_assoc=8 --mem-type=HMC_2500_1x32 --hmc-dev-vault-size=256MB -c ./tests/tes

[gem5-users] Re: encounter problems about cache options under SE mode

2020-04-27 Thread yangyuqing--- via gem5-users
The version of gem5 I use is not the newest version because the simulator is developed in 2018 which is based on gem5. I want to know why followings happen: 1.When I use DDR3_1600_8x8 instead of HMC_2500_1x32, the program runs correctly. 2.When I use HMC_2500_1x32, the program runs correctly whe

[gem5-users] GEM5 SE mode with HMC memory and cache run fails with "panic condition !(pkt->isRead() || pkt->isWrite()) occurred: Should only see read and writes at memory controller"

2020-04-28 Thread yangyuqing--- via gem5-users
If i use this command, problem happens: ./build/X86/gem5.opt configs/example/se.py --fast-forward 2290 -I 10 --cpu-type=TimingSimpleCPU --cpu-clock=1GHz --caches --l2cache --l1d_size=64kB --l1i_size=32kB --l2_size=256kB --l1d_assoc=8 --l1i_assoc=8 --mem-type=HMC_2500_1x32 --hmc-dev-

[gem5-users] A problem about using pseudo instruction in my own program

2020-04-29 Thread yangyuqing--- via gem5-users
I define a new pseudo instruction, but i can not get its correct return value in my program. The part of code is shown below. In include/gem5/m5ops.h: bool PIM(uint64_t in1, uint64_t in2, uint64_t out1, int kernel_id); In pseudo_inst.cc: case M5OP_RESERVED4: PIM(tc, args[0], args[1], args

[gem5-users] Re: A problem about using pseudo instruction in my own program

2020-04-29 Thread yangyuqing--- via gem5-users
Hi,I follow your advice and have solved the problem successfully. Thanks a lot for your help. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)

[gem5-users] warn: DRAM device capacity (1024 Mbytes) does not match the address range assigned (256 Mbytes)

2020-04-29 Thread yangyuqing--- via gem5-users
Dear all, who knows how to solve this warn when running programs? Btw, it seems not to make any effect on the correctness of programs. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_

[gem5-users] a problem about memory access latency of HMC

2020-06-05 Thread yangyuqing--- via gem5-users
I'm using HMC as my memory in my system. And I found a problem that once a simobject sent a read request, the latency of the response was different. I print out the DRAM trace. 1. if a read request is processed by dramctrl as follow, the latency is longer. 377334000: system.hmc_dev.mem_ctrls00: r

[gem5-users] Re: a problem about memory access latency of HMC

2020-06-05 Thread yangyuqing--- via gem5-users
Jason, Thanks a lot for your answer. I use following code to send a read request to HMC in my own simObject. Request::Flags flags = 0; RequestPtr req = make_shared(regs[toProc].first, 8, flags, 0 ); PacketPtr pkt = new Packet(req, MemCmd::PIMRead); uint8_t* empty = new uint8_t[8]; pkt->dataDynami

[gem5-users] scons error:invalid use of incomplete type 'class System'

2021-02-25 Thread yangyuqing--- via gem5-users
I use gem5 20 on ubuntu 20.04. I try to add some new features to gem5, but I do not damage class system. When I run scons, errors occurs like following: In file included from /usr/include/c++/9/cassert:44, from build/X86/mem/cache/write_queue_entry.hh:49, from bui