[gem5-users] aarch64 (armv8-a) - question on adding a new processor support

functional units, so that gem5 can simulate our processor more accurately. Please provide some starting pointers on the same. 3. What other factors should be considered while adding new processor support, assuming that we may want to upstream our work to gem5 organization later.

[gem5-users] size of committedInsts used in calculation of ipc

fferent flags but could not succeed. Thanks. -- with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] parent class of DerivO3CPU

two different files have different definition for DerivO3CPU. Thanks. with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] comparing number of instruction of the same binary on gem5 & juno (using linux perf)

u.numCycles22634230 system.cpu.ipc 0.446321 (10102135/22634230 = 0.446321) Thanks for your time in advance. -- with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailm

Re: [gem5-users] Stats.txt information misleading

I doubt step2 (restoring from checkpoint). Isn't options --checkpoint-restore & --restore-with-cpu required for restoring from checkpoint. http://www.m5sim.org/Checkpoints Thanks. -- with regards, Virendra Kumar Pathak ___ gem5-users mai

Re: [gem5-users] CPU Configuration

with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] LSQ bottleneck when using X86 TSO

d to add the support of splitting stores instructions in "store-address" & "store-data" micro-ops. If I am not wrong on above, could you please give some high level guidance on what changes need to be done to achieve it. Thanks for you

Re: [gem5-users] aarch64 (armv8-a) - question on adding a new processor support

Hi Fernando, Thanks for the information. -- with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] CPU Configuration

Thanks for your time in advance. -- with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] InOrder ARM processor

Hi Ali Saidi, I have a similar question w.r.t gem5 O3 cpu model. How close is existing O3 model with respect to cortex a57 (64 bit) say ARM juno board? A high level comment would be appreciable. -- with regards, Virendra Kumar Pathak ___ gem5-users

Re: [gem5-users] CPU Configuration

omething? Could you please explain what "Make IQ able to handle multiple FU pools." means ? Thanks in advance for your time and patience. -- with regards, Virendra Kumar Pathak 0001-adding-decodeQueue-between-decode-and-rename.patch Descri

Re: [gem5-users] Stats.txt information misleading

below is the code - FullO3CPU::tick() { DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); assert(!switchedOut()); assert(drainState() != DrainState::Drained); ++numCycles; ppCycles->notify(1); ... ... Thanks. -- with regards, Virendra

[gem5-users] arm - ruby model failed at run time

o the code and found, unlike x86, makeArmSystem() do not initialize test_sys._dma_ports. Am I doing some mistake? Please help in resolving this issue. Thanks in advance for your time. -- with regards, Virendra Kumar Pathak ___ gem5-users mailing list

Re: [gem5-users] arm - ruby model failed at run time

one please confirm if issue is still present or it was solved in recent commits. Thanks in advance for you time. On 16 November 2015 at 20:13, Virendra Kumar Pathak wrote: > Hi gem5 users, > > Do ruby memory model works with arm in gem5 ? > > I am following below steps to compile and

[gem5-users] store conditional instruction handling in rename stage

e; else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && !inst->isSerializeHandled()) { renamedSerializing++; inst->setSerializeHandled(); serializeAfter(insts_to_rename, tid); } Thanks in advance for your time. --

Re: [gem5-users] arm - ruby model failed at run time

time. -- with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] FATAL error: unimplemented syscall set_tid_address

binary. http://www.mail-archive.com/gem5-users%40gem5.org/msg12164.html Thanks. -- with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] store conditional instructions not coming in O3PipeView

* *O3PipeView:dispatch:152181* *O3PipeView:issue:152181* *O3PipeView:complete:152514* *O3PipeView:retire:153180:store:0* Thanks in advance for your time. -- with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http