Re: [gem5-users] Want to add wiki for gem5 and eclipse development

You don't need any permission to edit the wiki... just click "Create Account" in the upper right and go for it. I strongly encourage you to put as much information as possible on the wiki directly so that (1) others can easily update/extend it and (2) we don't have to worry about any links going s

Re: [gem5-users] [gem5-dev] Mem Request Assertion fail [VALID_VADDR]

Writebacks do not have virtual addresses, as only the physical address is available in the cache tag. Steve On Fri, Apr 17, 2015 at 10:59 AM, Vinayak Bhargav Srinath wrote: > Hi folks, > > Currently, using a work around to prevent this failure incase there is no > Vaddr in the pkt->req by using

Re: [gem5-users] Technical report

Hi Tod, Thanks for being willing to share your experiences and configurations. The best way to do that is via the gem5 wiki; you can just create an account and then create a page to hold your information. Let us know if you have any questions. Thanks, Steve On Sun, May 3, 2015 at 5:16 AM, To

Re: [gem5-users] Gem5 boot time

gem5 is a simulator, not an emulator. Nevertheless, those times seem very long, unless you are using the detailed CPU model or something. Steve On May 5, 2015 9:58 PM, "Junaid Shuja" wrote: > Hi, > I was trying to find out boot time of different gem5 (opt, fast) build > options. The gem5.opt boo

Re: [gem5-users] How does scheduler work in SE mode?

There is no scheduler in SE mode. The number of hardware thread contexts (which is the same as the number of cores, unless you have SMT enabled in O3) must be >= the number of software threads that get created, so each software thread gets its own dedicated hardware context and no scheduling is ne

Re: [gem5-users] How does scheduler work in SE mode?

on is it possible to write/make a scheduler as a new > component by myself? It just does the simplest scheduling work. > > Thanks! > > M.Y. Lin > > > On Sun, 14 Jun 2015 14:06:45 +, Steve Reinhardt wrote > > There is no scheduler in SE mode. The number of hardware

[gem5-users] gem5 workshop slides posted

Hi everyone, I've uploaded and linked the presentations from last week's gem5 user workshop on the wiki page: http://www.gem5.org/User_workshop_2015#Final_Program Cong Ma has promised to send updated slides, so I have not posted his talk yet. Please let me know if there are any problems with any

Re: [gem5-users] SE mode Peripherals

You can certainly include devices in your system configuration regardless of whether you're using SE or FS mode. Without a device driver, though, it's tricky to actually use use device, unless you've explicitly designed the device for user-mode access, or if your application has its own device driv

Re: [gem5-users] SE mode Peripherals

ication among the entire > system, I was planning to add an USB drive and monitor its communication, > do you think it's possible to implement it? > I really appreciate your help. > > Best, > Yuting > > On Jun 26, 2015, at 4:15 PM, Steve Reinhardt wrote: > > You

Re: [gem5-users] SE mode Peripherals

or this, which > I'm not very sure how to do it. Is it possible if you can provide me with > some examples? I'm really sorry about all these basic questions, I'm still > very new to gem5. > > Thank you very much. > Best, > Cao > > > > On Jun 28, 2015, a

Re: [gem5-users] dual system simulation using multiple event queues

Sorry, I had forgotten that getting the multi-queue simulation to run requires an additional patch that's (1) not committed and (2) currently only works for x86. See http://reviews.gem5.org/r/2320. So I guess the question of whether pd-gem5 works with multithreading is something we can just ponder

Re: [gem5-users] Binary Translation in gem5

You are right that each instruction execution is a separate call. There is no binary translation being done. Steve On Mon, Jul 13, 2015 at 11:45 PM Abhishek Joshi wrote: > Hi, > Can anyone please tell if binary translation is implemented in gem5? I > have looked through the code and I am aware

Re: [gem5-users] Debugging in gdb

If you're just trying to generate a checkpoint at a particular point in a program, you can also insert a pseudo-instruction in the program to cause a checkpoint to be generated without having to figure out the PC value. Steve On Wed, Aug 5, 2015 at 11:34 AM Lingxiao Jia wrote: > Thanks, Patric

Re: [gem5-users] Debugging in gdb

nks, Steve. I know the pseudo-instruction stuff, but I do want to > generate checkpoint at certain PC. > > On Thu, Aug 6, 2015 at 3:38 AM, Steve Reinhardt wrote: > >> If you're just trying to generate a checkpoint at a particular point in a >> program, you can also insert

Re: [gem5-users] Sources of In-determinism in Full System Simulators

Even with x86 you should be seeing deterministic results. If you are regularly seeing inconsistencies, you can try running two copies with debug tracing (I suggest Exec,ExecMacro,Cache as a starting set of flags) and comparing their output with util/tracdiff to see where they diverge. Steve On T

Re: [gem5-users] Sources of In-determinism in Full System Simulators

epeated runs. > So as andreas mentioned this must be introduced by this specific benchmark. > > Thanks Andreas and Steve. > > On Thu, Aug 13, 2015 at 1:22 PM, Steve Reinhardt wrote: > >> Even with x86 you should be seeing deterministic results. If you are >> regularly

Re: [gem5-users] Remote debugging using gdb

You can call functions from gdb, but most functions are not designed to be called from gdb. What arguments does the function expect, and what arguments are you providing? On Mon, Aug 24, 2015 at 8:13 AM Lingxiao Jia wrote: > Hi all, > > Can anyone help with this issue? I am still not finding ho

Re: [gem5-users] Remote debugging using gdb

ctly using gdb in SE mode, and I want to dump stats and create > checkpoints at breakpoints. However, this doesn't work and gem5 panics and > reports: page table fault when accessing virtual address 0... I don't > know if I can call function in remote debugging session. Thanks. &

Re: [gem5-users] calcEA() function crashes

Which pointer is null? Are you sure it's a memory instruction, and that all the dependencies are satisfied? On Mon, Aug 31, 2015 at 11:42 AM Abhishek Rajgadia wrote: > Dear All, > I am trying to compute effective address by calling calcEA() given in > src/cpu/o3/dyn_inst.hh . But when i call t

Re: [gem5-users] [gem5-dev] Dummy process support

Hi Jyothish, Can you elaborate on what you're trying to do? How do you end up with a thread context that has no process pointer? When does that thread context get used? Thanks, Steve On Fri, Sep 18, 2015 at 3:30 AM Jyothish Soman wrote: > Just in case anyone faces this later, this made it w

Re: [gem5-users] LSQ bottleneck when using X86 TSO

your proposal to have separate store-address and store-data micro-ops though. I'd have to look more closely at the code, and unfortunately I don't have time to do that right now. Regards, Steve On Mon, Nov 2, 2015 at 4:12 AM Virendra Kumar Pathak < kumarvir.pat...@gmail.com> wrote:

Re: [gem5-users] Simple timing CPU hangs for parsec x86 simuatlion?

Try it with this patch: http://reviews.gem5.org/r/2691 You may also need 3290 & 3291, if the code uses cmpxchg. Steve On Thu, Jan 28, 2016 at 6:47 AM Timothy Chong wrote: > Hello all, > > I’m trying to run simple timing FS simulation with parsec x86 with 16 > cores. My simulation gets stuck b

Re: [gem5-users] Address Translation wiki page is empty

There was an effort several years ago to reorganize the documentation on the wiki which led to creating an outline, but then the effort stalled and parts of the outline were not filled in. I expect that's what happened here. If you have specific questions about address translation, feel free to a

Re: [gem5-users] Address Translation wiki page is empty

> >> const Addr PageShift = 13; >> > > Is this the correct place to look into ? > > > On Sat, Feb 6, 2016 at 11:54 PM, Steve Reinhardt wrote: > >> There was an effort several years ago to reorganize the documentation on >> the wiki which led to creatin

Re: [gem5-users] About UpgradeReq and write hit

Upgrade requests are used on a write to a shared copy, to upgrade that copy's state from shared (read-only) to writable. They're generally treated as invalidations. A write hit implies that a cache has an exclusive copy, so it knows that there's no need to send invalidations to lower levels. Ther

Re: [gem5-users] About UpgradeReq and write hit

I 0 0 0 >> >> For a shared block, according to the explanation of wikipedia, they can >> be "dirty" (Here the 'dirty" is with respect to memory), We probably >> have several modified copies. But gem5 think they are a

Re: [gem5-users] About UpgradeReq and write hit

>> >> >> >> See, that's why when the returned resp packet arrives at L1, its >> address(pkt->getAddr()) can't be equal to the target's packet's address >> (&#

Re: [gem5-users] Simulating two X86 machines

Thanks!! I really appreciate you posting these directions to the mailing list. If you don't mind, it would be even more helpful if we integrated the necessary changes into the code repository (assuming they don't cause any problems in other situations) and added the necessary instructions (and th

Re: [gem5-users] I/O device in SE mode

Sure. The example config scripts don't instantiate standard I/O devices like hard drives in SE mode because they're not needed, but you can still do it. The recently added GPU model is a good example of something that has some device-like characteristics but is used in SE mode. There are a couple

Re: [gem5-users] x86 cmpxchg support

Both cmpxchg8b and cmpxchg16b are implemented, see: http://grok.gem5.org/xref/gem5/src/arch/x86/isa/insts/general_purpose/semaphores.py#130 This code does rely on the ability to do locked RMWs in the cache, which works fine out of the box for the AtomicSimple and TimingSimple CPUs, but requires th

Re: [gem5-users] x86 cmpxchg support

Yes. The constraints I mentioned on locked RMWs (and associated patch) only apply to classic caches; ruby already supports locked RMWs in all cases. Steve On Tue, Apr 19, 2016 at 3:22 PM Tanmay Gangwani wrote: > Thanks. And do both ruby and classical memory subsystem support this? > __

[gem5-users] anyone out there using EIO trace support?

If not, we are likely to drop it... so speak up now if you care! Thanks, Steve ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Micro-op Data Dependency

There are really two issues here, I think: 1. Managing the ordering of the two micro-ops in the pipeline, which seems to be the issue you're facing. 2. Providing atomicity when you have multiple cores. I'm surprised you're having problems with #1, because that's the easy part. I'd assume that you

Re: [gem5-users] Micro-op Data Dependency

I'm still confused about the problems you're having. Stores should never be executed speculatively in O3, even without the non-speculative flag. Also, assuming the store micro-op reads a register that is written by the load micro-op, then that true data dependence through the intermediate register

Re: [gem5-users] Micro-op Data Dependency

. With this code, it works with > minor model, but the final calculated value in the modify-write micro-op > never gets written at the end of the instruction in the O3 model. > > > On Fri, Jul 29, 2016 at 2:50 PM, Steve Reinhardt wrote: > >> I'm still confused about

Re: [gem5-users] Micro-op Data Dependency

the > minor CPU model problem I described before. > > No, most of the ISA is not microcoded. In fact, as I said, these RMW > instructions are not specified to be microcoded by the ISA, but since they > each have two memory transactions they didn't appear to work unless I split >

Re: [gem5-users] Micro-op Data Dependency

es is > "setIntRegOperand," which takes indices into _destRegIdx rather than > register indices. > > On Mon, Aug 1, 2016 at 10:58 AM, Steve Reinhardt wrote: > >> You don't need to worry about the size of the bitfield in the instruction >> encoding, because the tem

Re: [gem5-users] [gem5-dev] Removal of ALPHA from gem5

I agree with Alex: the ISA description system was designed for Alpha, and it remains the purest example of how it was intended to be used, so I think there's some value in keeping it around for that. To me, it should boil down to a cost/benefit consideration. I agree that the benefits are not that

[gem5-users] more on Nate Binkert

Following up on Jason's note to the gem5-dev list, I wanted to share a brief post I wrote for the SIGARCH blog: https://www.sigarch.org/remembering-nathan-binkert I think it's safe to say that gem5 would not exist if it were not for Nate. About 15 years ago, when he was my PhD student at Michigan,

Re: [gem5-users] Zero cost print for debugging/profiling code in se.py

The PCEventQueue in src/cpu/pc_event.hh allows you to trigger events on the execution of particular PCs. The difficulty of course is mapping source code to PCs. You would also not be able to pass any data to the event. Using an m5op would incur some small overhead for fetching & executing the op

Re: [gem5-users] gem5 GUI?

There is no GUI for configuration, and I know of no plans to add one. Having worked with SimNow a bit, I can tell you that the charm of a GUI fades pretty rapidly when you want to build complex systems with lots of cores. That said, I know it does make the learning curve a little less steep.if so

Re: [gem5-users] Can Any one Suggest any good tool to Analyze the Source code

The .cc files are not "managed C++" (whatever that is), they're just plain old C++. If your Eclipse or whatever doesn't recognize .cc files as plain C++, you just need to update its mapping from extensions to languages. For local analysis, I use cscope; I think it's available as an ubuntu package

Re: [gem5-users] Gem5 compiling error

I'm even further behind than Andreas, but I'm curious about the situation here. It's been a while, but last time I checked, compiling the x86 decoder with gcc took about 1GB of RAM (definitely <1.5GB). If something has happened to the code and/or gcc that really makes it take much more than that,

Re: [gem5-users] Gem5 compiling error

Good point... I was probably compiling gem5.debug not gem5.opt. Perhaps we should implement some of the features we came up with long ago to split the decoder.cc output into multiple files. Steve On Mon, Jan 7, 2013 at 9:52 AM, Nilay Vaish wrote: > On Mon, 7 Jan 2013, Steve Reinhardt wr

Re: [gem5-users] Running benchmark on FS X86 : Assertion `!delayedResponse' failed.

My suggestion for debugging this is to use debug tracing to see how you got there. Since you know when the error happens, you can turn on tracing just a little bit in advance so you're not slowing down the whole simulation. So add soemthing like: --trace-start=506535900 --debug-flag=TLB,Ruby

Re: [gem5-users] config.ini doubt

The point of the config.ini is to give a very low level confirmation of the parameter settings so you can know what your simulation script is really doing. It's the equivalent of reading the assembly code to make sure your compiler isn't broken (well, not exactly, but close). Once you've confirme

Re: [gem5-users] Question about PacketQueue::scheduleSend

For events that are scheduled in the same cycle, we can use the event priorities to control relative ordering. Our initial assumption when we saw that the cache ack was occurring after the CPU's check of the store_in_flight flag was that it would just be a matter of changing the priorities, but th

Re: [gem5-users] Question about PacketQueue::scheduleSend

nd a >>>> request from the cache? What if there are buses on both sides of the cache? >>>> There are many similar situations in gem5. The only way the priorities >>>> would really help is if we at instantiation time managed to sort all events >>>> by splittin

Re: [gem5-users] LSQ full condition checked at rename - O3

It's really just modeling a simplified dispatcher, which stalls conservatively unless it knows it can dispatch the next instruction regardless of its type. We've made some changes internally at AMD to relax this, and will try to post them before too long. It's not terribly hard to change on your

[gem5-users] Internship developing network interface model

s and interests as they relate to this position in your email. I am ideally seeking someone who will be available for the summer, but will consider other schedules if necessary. Thanks, Steve Reinhardt AMD Research ___ gem5-users mailing list gem5-users

Re: [gem5-users] gem5 build problem

The quickest fix is to delete this line in src/SConscript: swig_env.Append(CCFLAGS='-Werror') Steve On Wed, Mar 20, 2013 at 7:52 PM, Tao Zhang wrote: > Dear all, > > When I built the latest gem5, the following compilation erros came up. > More interesting, it only happens when buiding ge

Re: [gem5-users] gem5 build problem

on. I just worried about there is any > issue for this compilation error. It looks weird. > > Anyway, thanks a lot! > > -Tao > > > On 03/20/2013 11:09 PM, Steve Reinhardt wrote: > > The quickest fix is to delete this line in src/SConscript: > > swig_env.Append(C

Re: [gem5-users] gem5 build problem

, '4.7') >= 0: > > new_env.Append(CXXFLAGS='-Wdelete-non-virtual-dtor') > > swig_env.Append(CCFLAGS='-Wno-maybe-uninitialized') > > ** ** > > ** ** > > ** ** > > *From:* gem5-users-boun...@gem5.

Re: [gem5-users] Behavior changed before/after enabling --debug-flags

You're right, it typically shouldn't. If your problem is something like a memory allocation bug (use after free, or something like that) then executing the DPRINTFs could change where it manifests itself. Steve On Wed, Apr 3, 2013 at 12:01 PM, Rio Xiangyu Dong wrote: > My modified code got an

[gem5-users] AMD full-time job opening, gem5 experience a plus

Hi everyone, I want to make you aware of a full-time Server Performance Modeling Engineer position that is open at AMD in Sunnyvale, CA. Familiarity with gem5 is a plus for this position, so I thought it would be relevant to the list. See the official posting for more details: https://amd.apply2

Re: [gem5-users] Thread switch

Hi Yanqi, It's hard to answer your question without more information about your situation. For example, are you running in full system mode or syscall emulation mode? Are you talking about threads on the same CPU, or on different CPUs? Steve On Tue, Jun 11, 2013 at 5:22 PM, Yanqi Zhou wrote

Re: [gem5-users] Thread switch

From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on > behalf of Steve Reinhardt [ste...@gmail.com] > *Sent:* Wednesday, June 12, 2013 3:43 PM > *To:* gem5 users mailing list > *Subject:* Re: [gem5-users] Thread switch > > Hi Yanqi, > > It's hard to

Re: [gem5-users] Thread switch

gem5-users] Thread switch > > Hi Steve, > I am running full system mode. Threads are on different CPUs. For instance > I allocate 4 CPUs for 4-thread programs. > Thanks, > Yanqi > -- > *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.or

Re: [gem5-users] Thread switch

ng cpu switch. What triggers the cpu switch in > gem5 by default? What happens to cpu1 if cpu0 is stalled for a long time > (due to a cache miss or something)? > > Yanqi > -- > *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on > beh

Re: [gem5-users] Thread switch

lls. Can you suggest a easy way to stall one cpu > without affecting another cpu? > Thanks, > Yanqi > -- > *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on > behalf of Steve Reinhardt [ste...@gmail.com] > *Sent:* Wednesday, Jun

Re: [gem5-users] Simulation of a complicated peripherals system

gem5 doesn't model things like PCI in detail, but you can tailor the bus model to have the bandwidth and latency you want to approximate the performance of a PCI link. There are several PCI DMA devices implemented, including a couple of different Ethernet NICs; see the src/dev directory. At this

Re: [gem5-users] Low IP for SPEC CPU 2006 benchmarks

The X86 support has primarily focused on getting the functionality correct. Performance modeling accuracy, particularly for the O3 model, has not been as big of a focus. There are some fixes in the pipeline here at AMD that we have not gotten to submitting publicly yet, so this should improve ove

Re: [gem5-users] About writebacks in cache_impl.cc

In the classic (non-Ruby) memory system, the cache hierarchy is non-inclusive, so demand misses go straight to the L1 cache. Blocks only get inserted in levels other than the L1 due to writebacks (and possibly prefetches, if you have a prefetcher associated with that level of cache). Steve On F

Re: [gem5-users] About writebacks in cache_impl.cc

can refer Achieving Non-Inclusive Cache Performance With Inclusive > Caches -- Temporal Locality Aware (TLA) Cache Management > Policies"<http://www.jaleels.org/ajaleel/publications/micro2010-tla.pdf>, > for clarification > > > On Fri, Jun 21, 2013 at 8:10 PM, Steve Re

Re: [gem5-users] About writebacks in cache_impl.cc

ccess method before the > calling to tags->accessBlock, I do this: > > bool isWriteback=false; > if (pkt->cmd == MemCmd::Writeback) > isWriteback=true; > > Later I use this flag for the tags->insertBlock method. > > > Best Regards > >

Re: [gem5-users] Beginning to understand GEM5 source code

Have you read this? http://gem5.org/Simulation_Scripts_Explained You don't have to recompile gem5 if you change the simulation scripts (basically anything under the configs directory). However, the code under the src directory (including python code) is compiled into the executable, so you do ha

Re: [gem5-users] gem5 stops making progress in some applications

Very strange... if it's not making progress, it must be livelocked, because otherwise you would hit the max_tick event and exit. You should be able to jump in with gdb, turn on a few trace flags, and see what's happening. If any of these are benchmarks that used to complete, you could use 'hg bis

Re: [gem5-users] Problems with extreme large tick numbers

Really large values like that tend to mean that your simulation is deadlocked, so few or no events get scheduled. There is a termination event scheduled at MaxTick to prevent the event queue from wrapping around to zero; that's 2^63-1, or 9223372036854775807. If you're actually seeing an event at

Re: [gem5-users] Problems with extreme large tick numbers

MaxTick&refs=&path=&hist= On Tue, Jul 9, 2013 at 8:19 AM, Andreas Hansson wrote: > MaxTick is unsigned these days so I would think it's 2^64 – 1. > > From: Steve Reinhardt > Reply-To: gem5 users mailing list > Date: Tuesday, 9 July 2013 16:16 > To: gem5 use

Re: [gem5-users] Gem5 incremental-build time

Arguably if you're not running enough jobs to justify a few minutes of link-time LTO overhead, you should probably be building gem5.debug or gem5.opt anyway... IIRC, the main purpose of --no-lto was to deal with platforms/systems where LTO was outrageously expensive (several tens of minutes, not ju

Re: [gem5-users] Python Object Attributes

a) You missed a dot... it's referring to the "port" on the object "system.physmem" b) "m5" is a python package, not an object On Sat, Jul 13, 2013 at 8:04 AM, Zheng Wu wrote: > Hi All, > > I am reading the configuration scripts in python and I am having a > difficult time finding all the attr

Re: [gem5-users] Can we use Emacs for Gem5 ?

I'm not sure exactly what you're asking, but I do almost all my gem5 debugging using xemacs gdb-mode. It works fine for the C++ parts. You can use pdb on the python parts, but sometimes I find it's easier just to add print statements when debugging python. Steve On Fri, Aug 9, 2013 at 4:58 AM,

Re: [gem5-users] Multicore programs

If you're in FS mode, then thread scheduling is controlled by Linux. You can run as many programs as you want, just like on a real Linux system, and if you have more runnable threads than cores, they will be time-sliced by the kernel using its internal thread scheduling algorithm. Your ability to

Re: [gem5-users] Multicore programs

./astar & taskset -pc 1 ./bzip > but the program terminates early. > Can you show me the exact command I should use? > > Thanks, > Yanqi > -- > *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on > behalf of Steve Reinhardt [ste.

Re: [gem5-users] IPC

Are you using the default configuration parameters? Are you using the classic cache model or Ruby? There are a handful of performance model issues with the combination of O3 and x86, particularly if you're using Ruby. We have some patches internally here at AMD that we are working to clean up and

[gem5-users] internship positions at AMD Research

AMD Research is seeking student interns interested in extending and enhancing gem5 for projects focusing on the detailed design of high-performance network interfaces. We are looking for candidates who have hands-on experience with gem5, as well as one or more of the following: - I/O device model

Re: [gem5-users] How does iocache work?

> Hi, > > I am confused about the way iocache works. I saw the previous explanation : > > > * On Nov 7, 2008, at 7:28 PM, Steve Reinhardt wrote: > Yes, the whole > reason for having an IO cache is to make device > accesses work in coherent > space. An IO cache isn&#

Re: [gem5-users] m5.opt: error: no such option: --trace-file

The --trace-file option was recently renamed to --debug-file to be consistent with other arguments. All the --trace-* arguments are now --debug-*. Steve On Wed, Nov 27, 2013 at 3:57 PM, Xing Niu wrote: > Hi, > > When running GEM5 + Dramsim2 + PARSEC, I encounter a problem: m5.opt: > error: n

Re: [gem5-users] Accelerator in Gem5

Take a look at the existing devices in src/dev. A lot of the functionality you need is encapsulated in the base classes in that directory. See http://www.gem5.org/docs/html/classPioDevice.html for a class hierarchy chart. Steve On Fri, Dec 20, 2013 at 12:59 AM, Erfan Azarkhish wrote: > Dear

Re: [gem5-users] Calling a C++ function in Python

What have you tried and what problems are you having? It should just be a matter of calling 'obj.addChild(x)' on your ChildStates object 'obj'. It looks like you've figured most of this out already, but a lot of the current mechanism was added in this changeset (see particularly the comments in t

Re: [gem5-users] Calling a C++ function in Python

done. > > One day I may add some information to the wiki, but I am a tad busy now. > > Best regards, > > Alex Tomala > -- > *From:* Steve Reinhardt > *To:* Alex Tomala ; gem5 users mailing list < > gem5-users@gem5.org> > *Sent:* Thursday, January

Re: [gem5-users] Calling a C++ function in Python

_ > % (self.__class__.__name__, attr) > AttributeError: object 'ChildStates' has no attribute 'addChild' > > Best regards, > > Alex Tomala > -- > *From:* Steve Reinhardt > *To:* Alex Tomala > *Cc:* gem5 users m

Re: [gem5-users] Calling a C++ function in Python

s your problem here. Steve On Thu, Jan 2, 2014 at 3:48 PM, Alex Tomala wrote: > The method seems to show up in both files, which I have attached to this > email. Looking over the SWIG documentation briefly, I found no problems > with the files. > > - Alex > > -

Re: [gem5-users] Calling a C++ function in Python

n and add the list to the ChildStates > as a parameter. I am wondering how the python list can be converted to a > C++ vector object, as I do not know how. > > Best regards, > > Alex > > -- > *From:* Steve Reinhardt > *To:* Alex Tomala

Re: [gem5-users] Calling a C++ function in Python

ilar way as an > integer would be done, like this: > > example_int = param.Int("Description") > example_vector = param.VectorParam("Description") > > Best regards, > > Alex Tomala > > -- > *From:* Steve Reinhardt > *To:*

Re: [gem5-users] Questions regarding modifying builds in gem5

You should not modify files under the build directory. The source files you see there are either auto-generated code or just links to the ones under src. SCons automatically tracks dependencies, so if you make changes to the source files under src, then re-running the scons command will take the

Re: [gem5-users] Modifying I/O APIC Address range

The current APIC address mapping is tied to where the kernel expects to see it, i.e., where it is on the standard PC platform. If you want to support larger memories, you'd have to figure out what the physical address map looks like for PCs with >3GB. Steve On Mon, Jan 13, 2014 at 3:56 AM, Ahma

Re: [gem5-users] Tracing options in gem5 dev version as compared to gem5-stable

Those options were renamed --debug-file and --debug-start at some point, but that rename hasn't made it into the stable version yet. Steve On Mon, Jan 13, 2014 at 4:24 PM, Aditya Deshpande < adityamdeshpa...@gmail.com> wrote: > Hi, > > I was using gem5-stable version, the build had a --trace-fi

Re: [gem5-users] /Build Directory not created during istallation

The build directory will not be created until the first time you run scons. Steve On Tue, Jan 14, 2014 at 3:18 AM, abbas abdolali pour wrote: > Hello all, > > Previously I've installed the GEM5 on centOs and all directories and other > folders are exists inside the gem5 folder like /build and I

Re: [gem5-users] Wiki problem

Yes, I can reproduce that... thanks for pointing it out. Steve On Wed, Jan 15, 2014 at 9:43 AM, Patrick wrote: > Hello, > > Some of the pages in the documentation section of the wiki appear not to > be working. For example, I am unable to access the "Introduction" page > under the "Getting St

Re: [gem5-users] The same workload for each core will be assigned to different physical addresses in a multicore system

Yes, in SE multicore mode you can either run multithreaded workloads (where all threads share the same memory) or multiprogrammed workloads (where each thread has its own memory). Right now there's no facility for sharing part of the workload but not all of it (e.g., just the binary). That could

Re: [gem5-users] cache, access, handleFill, satisfyCpuSideRequest, memcpy

std::memcpy(blk->data, pkt->getPtr(), blkSize) copies an entire cache block, which is what you want if you are receiving a cache miss response (as in handleFill) or processing a writeback (as in access). pkt->writeDataToBlock(blk->data, blkSize) handles writes that are smaller than a cache block,

Re: [gem5-users] redirect output of a simulated program in FS mode

You can use the '-d' option to put all of the output files in a different directory for each run. Steve On Fri, Feb 7, 2014 at 9:13 PM, Tod wrote: > It would be pretty easier and nicer, if you write a shell script that > do many simulations for you in a loop, then you can copy the generated

Re: [gem5-users] Question about GEM5

If you're in syscall emulation mode, each workload is treated completely independently. So for your example of 2X and 5Y benchmarks, you're really running 7 independent benchmarks from gem5's point of view. Unfortunately, this leads to some inaccuracy, since things like code that would be shared a

Re: [gem5-users] x86 full system dual

There's no fundamental reason it shouldn't work, though it likely hasn't been tested. It's just a matter of adding a NIC to the PCI bus in an x86 system (if there isn't already one there), using the existing dual-node framework to instantiate two of those systems, and hooking up the two NICs with

Re: [gem5-users] Reduced L2-Cache-Size leads to segmentation fault in ALPHA_FS

I just re-ran the ALPHA_FS O3 boot test with a 512kB L2 and it worked (the test of course failed, since the statistics change, but the simulated system booted fine). Basically I made this change: diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py --- a/tests/configs/tsunami-o3

Re: [gem5-users] Reduced L2-Cache-Size leads to segmentation fault in ALPHA_FS

, 2011 at 2:59 PM, Steve Reinhardt wrote: > I just re-ran the ALPHA_FS O3 boot test with a 512kB L2 and it worked (the > test of course failed, since the statistics change, but the simulated system > booted fine). > > Basically I made this change: > > diff --git a/tests/configs/

Re: [gem5-users] Barrelfish on gem5

Hi Tim, This is extremely cool. Thanks for letting us know! Steve On Mon, Jul 11, 2011 at 2:52 AM, Tim Harris (RESEARCH) < thar...@microsoft.com> wrote: > Hi, > > ** ** > > I thought other folk might be interested to know that we’ve included > support for running on gem5 in the most recen

Re: [gem5-users] rebuilding gem5 from scratch

rm -rf build On Tue, Jul 26, 2011 at 7:09 AM, Mahmood Naderan wrote: > Hi > how can I do "make clean" in gem5 and rebuild from scratch? > -- > // Naderan *Mahmood; > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/

Re: [gem5-users] Reduced L2-Cache-Size leads to segmentation fault in ALPHA_FS

Could you send these changes as a patch to make it easier for us to reproduce? Thanks, Steve On Tue, Jul 19, 2011 at 11:06 PM, Fabian Oboril wrote: > Here we go: > > in AlphaTLB.py > TLBs: 128 entries for each (D and I) > > in O3CPU.py > fetchWidth = 4 > decodeWidth = 4 > renameWidth = 4 > dis

  1   2   3   >