[gem5-users] How to classify op_class for x86 macoops

Hi Ali, I am a new user of gem5. I want to classify the op_class for x86 . I searched in the archive, and I saw you answering the question corresponding to similar question. It seems this work is well done for ARM. But how could that be done for x86, and for the macroops. Thanks a lot. Cheers, -J

[gem5-users] Where is the source code for tracking program pointer?

Hi All, I am very new to computer architecture simulator and is looking into gem5. I want to track the program counter under SE mode. Although I can do that via debug options, I want to know where in the source code this work actually gets done. I am using the atomic simple cpu mode. I could not f

[gem5-users] Where to readout the trace data?

Hi All, I am looking into gem5 src code but cannot figure out where the trace data is dealt with in the src code. I find some object called tracedata in cpu/simple/base.cc. I am wondering is this where all the traces are stored? And how it is read out by other function. Thanks a lot. Regards, -J

[gem5-users] Is there a SIMD unit for x86 in gem5

Hi All, Anybody know is there a SIMD unit in gem5 for x86? Or I need to implement it myself? Thanks, -Jacob ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] X86 O3 instruction fetch problem

Hi All, I am looking into the fetching stage for X86 O3. I have one question. For ordinary PC advancing without prediction or branch, lets say the current PC is: 0x4120a4.0 while the nextPC associated with the same DynInst is 4120a5.1 Why the actual PC fetched next will be 0x4120a4.1 instead of 41

Re: [gem5-users] X86 O3 instruction fetch problem

One more question will be is the nextPC associated with the DynInst the physically next instruction stored after the current one, or it is just predicted by some units?? On Thu, Oct 25, 2012 at 8:14 PM, Shen Yiran wrote: > Hi All, > > I am looking into the fetching stage for X86 O3. I