Hi!
I am currently using gem5 to develop and evaluate HPC Co-processors in
ARM-based systems. Most of such accelerators require direct access to
the memory, and have to be able to translate memory addresses from the
virtual address space to the physical address space. For doing so, I
have imp
Hi,
I am trying to use Huge pages (as big as 1GB) in gem5, but there seems
to be little to none documentation about the subject.
Does anyone know how to change the page size?
I am using the ARM ISA, in case it matters.
Thanks in advance!
Kind regards
--
Joao Vieira
ECE PhD Student at Tecn
he page_size.hh file though
> this has never been tested and it might not work without some adjustments
>
> Giacomo
>
> From: João Vieira via gem5-users
> Date: Tuesday, 22 March 2022 at 15:13
> To: gem5-users@gem5.org
> Cc: Nuno Roma , Pedro Tomás ,
> g...@deec.uc.p
Hi,
I am trying to limit the memory used by Linux so that I am left with
some physically addressable memory to use with accelerators in FS mode.
In physical systems, to do this, it suffices to boot the kernel with the
argument "mem=MAX_MEM", where MAX_MEM represents the maximum memory that
L
s != [] in
set_kernel_disk_workload, the only arguments added are the ones
specified in that list!
Is this a feature or a bug? I was expecting the optional kernel
arguments to be ADDED to the default arguments, and not replace them...
Kind regards,
Joao Vieira
On 24/01/23 12:10, João Vieir
Hi,
I am trying to run a RISC-V FS simulation in gem5 using the provided
kernel and image, but the system seems to get stuck at login (see below).
At first, I thought there was something wrong with my simulation script,
but then I tried to run the example
(configs/example/gem5_library/riscv-
Hi,
I am taking some performance results using In-Order x86, ARM, and RISC-V
CPUs in gem5, and I was wondering where to find the number of
implemented pipeline stages for each architecture. I have looked into
the simulation output files and I am having some difficulty locating
this informatio
##Pipeline-stages
In addition, other cpu stage implementations can be found!
And as far as I know, you have to make a new cpu to implement other
than the basic stage provided by Gem5.
Regards,
Haseung
2023년 3월 13일 (월) 오후 8:07, João Vieira via gem5-users
님이 작성:
Hi,
I am taking some
