Hi Haseung,
Thank you for your quick reply! I am actually using the TimingSimpleCPU
and the MinorCPU, but I just saw that in the manual you pointed out
there is a section for each of the models.
Thank you a lot! :)
Kind regards,
Joao Vieira
On 13/03/23 17:05, 봉하승 wrote:
Hi Joao,
If it is an in-order, is it implemented by changing all path widths to
1 using o3cpu?
Or did you use AtomicSimpleCPU, TimingSimpleCPU, MinorCPU?
If your cpu-type is o3cpu, The basic pipeline configuration is shown
in the link below.
https://www.gem5.org/documentation/general_docs/cpu_models/O3CPU##Pipeline-stages
In addition, other cpu stage implementations can be found!
And as far as I know, you have to make a new cpu to implement other
than the basic stage provided by Gem5.
Regards,
Haseung
2023년 3월 13일 (월) 오후 8:07, João Vieira via gem5-users
<gem5-users@gem5.org>님이 작성:
Hi,
I am taking some performance results using In-Order x86, ARM, and
RISC-V
CPUs in gem5, and I was wondering where to find the number of
implemented pipeline stages for each architecture. I have looked into
the simulation output files and I am having some difficulty locating
this information.
Do you have some advice on how to check this?
Thanks in advance!
Kind regards,
Joao Vieira
--
Joao Vieira
ECE PhD Student at Tecnico Lisboa | INESC-ID, Portugal
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--
감사합니다.
봉하승 드림
--
Joao Vieira
ECE PhD Student at Tecnico Lisboa | INESC-ID, Portugal
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