[gem5-users] Core dumped ALPHA FS + RUBY

I have no problem to run parsec with ALPHA full system simulation, but when I add ruby and garnet network, execution was aborted for core dumped. Here I list the command I used and log information. Really appreciate if somebody can give me advice on how to run parsec FS with ruby network. Thank

Re: [gem5-users] Core dumped ALPHA FS + RUBY

X86_MESI_Two_Level with the appropriate images (x86 ones) and try again. Em terça-feira, 10 de março de 2015, Jianghao <mailto:guojh...@gmail.com>> escreveu: I have no problem to run parsec with ALPHA full system simulation, but when I add ruby and garnet network, execution was ab

Re: [gem5-users] NOC Network

ation. Doesn't this mean I cannot use detailed CPU with garnet? Thanks On 3/16/2015 5:37 PM, babak aghaei wrote: Hi Dear jianghao! plz let me know why you need to establish the NoC network? --- *Babak Aghaei **Ph.D

[gem5-users] Full system simulation and Ruby

Is there anybody who has successful experience to run ALPHA full system and Ruby? I try many different configurations and just cannot boot up the system. Is this doable or it's the wrong way? I am stuck here for several days and thanks for any advice. ___

[gem5-users] ARM instruction set

I have a questions about ARM ISA implementation. From the document, instruction "format" is basically a Python function to generate up to four pieces of C++ code. If it's nested format structure like following code, which one will be used, DataOp, ArmMultAndMultAcc or both for the multiply instr

Re: [gem5-users] ARM instruction set

as Cc appended to the name. Ali On Jun 24, 2013, at 4:13 PM, Jianghao <mailto:guojh...@gmail.com>> wrote: I have a questions about ARM ISA implementation. From the document, instruction "format" is basically a Python function to generate up to four pieces of C++ code. If it&#

[gem5-users] ARM execution trace

From following piece of trace, I guess at tick 1000 and 1500, these are micro ops executed at execution unit. My question is what type of ARM instruction will be translated into micro op? Can I find related information in code? Thanks 0: system.cpu T0 : 0x8880: mov.w fp, #0

[gem5-users] Instruction Execution Time

Is there any way I can trace instruction execution time at different pipeline stages? For example, an ARM instruction goes through fetch, decoding and may be waiting in issue queue for execution. Which part of code I should take a look for this timing information? __

[gem5-users] O3 Timing

Take the following from config.ini file, my understanding is here we defined 2 function units, both of them can execute IntMult and IntDiv type of instructions, and opLat defines how many ticks need to execute that instruction. Please correct me if my understanding is wrong. My confusion comes

Re: [gem5-users] O3 Timing

#x27;m not sure if gem5 will simulate the contention in issue queue. Thanks again for any information. Hope it helps. Arthur. Le 17/07/2013 03:03, Jianghao a écrit : Take the following from config.ini file, my understanding is here we defined 2 function units, both of them can execute I

[gem5-users] CPU Configuration

It's interesting to see following setting in config.ini file. Why there are 2 delay defined between decode and fetch stage? [system.cpu] type=DerivO3CPU decodeToFetchDelay=1 fetchToDecodeDelay=3 . . ___ gem5-users mailing list gem5-users@gem5.org http:/

Re: [gem5-users] O3 CPU Squash

xecution? Which code I should take a look about this? In various CPU design, branch speculative execution can be handled in different pipe stages, so I'm wondering how gem5 handle this in simulation. Thanks again for your advice. On 7/29/2013 5:50 PM, Xiangyang Guo wrote: Hi, Jiangha

[gem5-users] Statistics of Instruction Queue

Is it possible to get statistics of how many ticks between instructions enter instruction queue and leave instruction queue for execution in O3 model? Appreciate any advice on how to implement this. Thanks ___ gem5-users mailing list gem5-users@gem5.

[gem5-users] Instruction Statistics

Still need help to get statistics about average clock cycles instruction waiting in instruction queue before execution. Thanks Jianghao <http://www.mail-archive.com/search?l=gem5-users@gem5.org&q=from:%22Jianghao%22>Thu, 29 Aug 2013 07:57:18 -0700 <http://www.mail-archive.com/

[gem5-users] ARM Load Instruction

From benchmark instruction trace on ARM architecture, there are following load instructions ldr ldr.w ldrb.w For ldr, I assume it will load word by default, so what's meaning of ldr.w? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5si

[gem5-users] Context switch in gem5

I want to do some experiments to measure performance of different cache structures. Basically on a dual core ARM system, a single thread program bounces back and forth between two cores every n cycles, then we measure the performance with different cache structure. Is this possible using conte

[gem5-users] Simulation blocked for more than 120 seconds

I am running splash2 simulation on ALPHA full system with RUBY and GARNET network. There is no problem to bring up the system and start the simulation, but it hangs after a long time and gives me following message repeatedly. Anybody knows what's the problem? Thanks Freeing unused kernel memory: 2

[gem5-users] checkpoint with O3 cpu

>From my understanding, when we do checkpoint, gem5 will not save cache content. How about other status like branch history? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Stats.txt information misleading

I run ALPHA SE with detailed CPU mode. Step1: make a checkpoint after 10 insts build/ALPHA_MOESI_hammer/gem5.fast configs/example/se.py --cpu-type=detailed --caches --l2cache --l1i_size=32kB --l1d_size=32kB --l2_size=512kB -c ./benchmark -I 10 --checkpoint-dir m5out --checkpoint-at-end S

Re: [gem5-users] Stats.txt information misleading

Thanks Virendra. It works now. I have another question. When I restore from a checking point, the "system.cpu.numCycles" in stats.txt will be the clock cycle from the checking point, or from the beginning of program? On Fri, Oct 30, 2015 at 12:46 AM, Virendra Kumar Pathak < kumarvir.pat...@gma

[gem5-users] Checkingpoint Resume overhead

When we do the checkingpoint and resume later on same type of CPU, does the total execution cycles time overhead come from the cache and other resource warm up? From my understanding, the checkingpoint will not save those status information. I did an experiment on this. I run a benchmark program i

Re: [gem5-users] CPU Configuration

variable number of pipeline stages. > > Regards, > > -- > Fernando A. Endo, PhD student and researcher > > Université de Grenoble, UJF > France > > > > 2013/7/17 Jianghao > >> It's interesting to see following setting in config.ini file. >

[gem5-users] O3 CPU Squash

How is squash handled in gem5 o3 CPU? What's exactly done in squash? >From codes under src/cpu/o3, there are squash functions defined in different pipeline resources, like iew, inst_queue, lsq etc. Does this mean each part can initialize squash? In following code, when an instruction is squashed,

[gem5-users] non-standard trapping mode not supported

I downloaded the pre-compiled ALPHA cross compiler and compiled SPLASH 2 benchmark(uni-processor version). When I run the binary in gem5 SE mode, I got a lot of warning messages like warn: addt/sud f24,f22,f11: non-standard trapping mode not supported warn: subt/sud f11,f14,f27: non-standard t

[gem5-users] splash 2 configuration file not working

Anything missing in the default splash 2 configuration file under /configs/splash2? It gives me following error message. ./build/ARM/gem5.opt configs/splash2/run.py -b FFT -n 1 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 comp

[gem5-users] Instruction execution delay

Is there any way I can increase execution delay of some instructions? For example, if I want to increase delay for some specific ALPHA floating point instructions, where I can change it? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim

Re: [gem5-users] Instruction execution delay

t; > Amin > > > > On Wed, Sep 12, 2012 at 12:48 PM, Jianghao Guo wrote: > >> Is there any way I can increase execution delay of some instructions? >> For example, if I want to increase delay for some specific ALPHA floating >

[gem5-users] ARM Instruction Description

When I first took a look ALPHA instruction description in arm/isa/decoder.isa file, there are several different "format" for different type of instructions. While for ARM ISA, there is only one "format" named DataOp in the deocder file, even worse I don't know where to find definition like ArmMultA

Re: [gem5-users] ARM Instruction Description

on in > src/arch/arm. > > Hope this helps, > > Jason > > Sent from my Samsung Epic™ 4G > > > > Jianghao Guo wrote: > > > When I first took a look ALPHA instruction description in > arm/isa/decoder.isa file, there are several different "format" f

Re: [gem5-users] ARM Instruction Description

a > number of instructions to that particular op class (grep src/arch/arm/ for > the existing op class names to see how they're assigned). > > Ali > > > > On 20.09.2012 11:21, Jianghao Guo wrote: > > Thanks Jason. > I'm also curious about the op class definitio

Re: [gem5-users] About Codebench Courcery installtion and use with gem5 and benchmarks

You can use *gcc-arm-linux-gnueabi* in Ubuntu. On Tue, Sep 25, 2012 at 6:28 PM, Musharaf Hussain wrote: > Please anyone > > can explain about Codebench Courcery installtion and use with gem5 and > benchmarks. > I want to use it for ARM processor. I am at Ubuntu 12.04 desktop > workstation 8.0 V

[gem5-users] Cache Warm Up Overhead in Thread Migration

I'm interested in the cache warm up overhead after thread migrated to other core. After the trigger of thread migration, it seems an easy way to measure this overhead is to reset the cache to initial state and continue execution. Can we do this in gem5 and how to do it? Thanks _

[gem5-users] Full System Simulation Stuck

I'm running gem5 full system simulation with build/ARM/gem5.opt configs/example/fs.py --kernel=vmlinux.aarch64.20140821 --disk-image=aarch64-ubuntu-trusty-headless.img --dtb-filename=vexpress.aarch64.20140821.dtb -n 8 In m5term, it shows "m5 slave terminal: Ternimal 0", then stuck there. Fro

[gem5-users] Routing in Garnet Network

Where can I find detail information about the routing table in garnet? Does it support adaptive routing? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] how to support 8 cores for ARMv8 FS simulation

. On Fri, Jan 30, 2015 at 6:31 PM, Zehan Cui via gem5-users mailto:gem5-users@gem5.org>> wrote: not yet, I'm using 4 cores now On Sat, Jan 31, 2015 at 4:04 AM, Jianghao mailto:guojh...@gmail.com>> wrote: Have you solved the problem? I'm in a similar situatio

[gem5-users] NOC Network

In Mesh topology network, why there is requirement that the number of directories to be equal to the number of cpus? How to specify number of L2 caches connected to the NOC network? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.o

Re: [gem5-users] ARM full system simulation

Hi Andreas, Thank you for your quick reply. I really appreciate it. If I want to do some experiments with NOC network, it seems Ruby is the only choice, right? Otherwise I have to use bus connection as you mentioned. Does that support shared distributed L2 cache and directory coherence? Is t

[gem5-users] Weird Parsec Simulation Result

I followed the instruction from utexas to download full system image and parsec binary. Then start a test run with command : * build/ALPHA/gem5.opt configs/example/fs.py --disk-image=/home/jo/my-gem5/full-sy stem/parsec/linux-parsec-2-1-m5-with-test-inputs.img --kernel=/home/jo/my-gem5/f u

Re: [gem5-users] one cpu keeps executing "@flush_tlb_others+133"

Hi Andreas, Do you know is there any core number limitation for ARM full system simulation? I'd like to set up a 8 cores system with garnet network connection. Any reference I can take a look? Thanks On Mon, Jan 26, 2015 at 3:30 AM, Andreas Hansson via gem5-users < gem5-users@gem5.org> wrote: >