Hi
I my experience, the only way to change the supply voltage in McPAT is to
change the values in the macpat/cacti/technology.cc file. Make sure you change
the values for the technology (180/90/65/45/32 nm ) and device type
(HP/LSTP/LOP) you use in your XML input file. You need to rebuild McPAT
prices.txt is the output file. It will be produced by your run of the
blackscholes application.
Alexandru Iordan
From: Newton Singh
To: gem5-users@gem5.org
Sent: Monday, May 27, 2013 12:21 PM
Subject: Re: [gem5-users] Blackscholes: prices.txt file missing
Hello
I am using gem5 to run a MP full-system simulation with Alpha. I am interested
in profiling some applications in terms of instruction mix and for that reason
I
want to clarify something about the INT and FP instruction counts (total and
committed).
>From my experience there are a two "
?
- Original Message
From: Ali Saidi
To: gem5 users mailing list
Sent: Fri, July 22, 2011 8:47:45 AM
Subject: Re: [gem5-users] INT and FP counts
Int alu accesses is counting every register that has at least one integer
operand.
Ali
On Jul 21, 2011, at 5:40 AM, Iordan Alexandru wrote
Hello
I am trying to profile some applications that I am simulating in MP full-system
using Alpha ISA. I added a custom pseudoinstruction (using one of the reserved
opcodes) so I can signal from the application itself the moments of interest
when I should collect the stats. My first solution w
Hello
I have been having problems using the checkpoint feature in GEM5. I tried to
run a very simple scenario:
1. I launched the simulator with the command:
./build/ALPHA_FS/gem5.opt --outdir=test/ configs/example/fs.py -n 2 --caches
--l2cache
2. using m5term I created a checkpoint (witch was
Hello
Thank you for your reply.
Is there no way to get a valid checkpoint in a simulation with caches enabled?
Is there nothing that I can do (hack)?
Alexandru
From: Ali Saidi
To: Iordan Alexandru ; gem5 users mailing list
Sent: Tuesday, August 9, 2011 9
Hello
It depends a lot on what type of simulation you use (SE or FS) and what type of
CPU (AtomicSimple, DerivO3 etc).
I only simulate FS and first of all, to make sure that you only get the stats
for the application (and not booting the OS + application) you first need to
reset (or dumprese
Hello
You used both -s (standard switch) and --fast-forward flags. The -s flag forces
a cpu switch at the beginning of the simulation (Switch at instruction count:0)
and --fast-forward triggers another switch later in the execution (Switching
CPUS @ tick 512312). You can look into gem5/co
Hello
The --take-checkpoints flag needs 2 arguments. If you take a look at the help
information you will see something like this:
--take-checkpoints=TAKE_CHECKPOINTS
will take checkpoint at cycle M and every N
cycles thereafter
If you only want t
Hello
I know this was discussed before but I did not find anybody who actually make
it work. Just like others before me I am facing difficulties in implementing
the back and forth switch.
What I did so far:
- I added the following to the configs/common/Simulation.py (the red code is
what I ad
Hello
I also encountered the error you described. In my case it was caused by the
fact that the parameters at the system level (number_of_cores, number_of_L2s,
number_of_NoCs etc.) that had a value of 1 were not described afterwards in
detailed. I see in your XML that you have but no descripti
Hello
A very simple fix would be to disable the warnings for scons. You can do
this by editing the SConscript file in the src folder. Change the "Werror =
true" to "Werror=false" and comment
"swig_env.Append(CCFLAGS='-Werror').
Hope this works.
Happy holidays!
Alexandru
Most probably your program has less than 5 instructions, so the switch
is never triggered with -F 5.
Regards
Alexandru Iordan
From: Surya Narayanan
To: gem5-users
Sent: Wednesday, February 1, 2012 12:22 PM
Subject: Re: [gem5-users] Prog exi
Hello
If you are using the PARSEC suite from the University of Texas
(http://www.cs.utexas.edu/~parsec_m5/), then you should read their report
(http://www.cs.utexas.edu/~parsec_m5/TR-09-32.pdf) to understand how they
customized the benchmarks. They basically divided each application in 3
secti
Hello
I added a pseudo instruction to GEM5 and I want to dump the function profile
every time this pseudo-inst is called from my simulated application. The
problem is that my FS simulation ends with a segmentation fault error. The
backtrace in GDB shows the following:
#0 _Rb_tree_const_iter
Isn't that true only if you also add the RUBY=True option to compilation?
According to http://www.gem5.org/Status_Matrix, the x86 FS is marked "should
work" which basically means "some implementation required". Right?
From: Ankita (Garg) Goel
To: gem5 users m
Hello
I recently updated my repository (changeset: 8926:97f06a79b6f5) and now I am
unable to build GEM5. The funny thing is that I don't get any error. I tried
the default configuration (according to SConstruct this is
build/ALPHA/gem5.debug) and the ALPHA_MOESI_CMP_directory but the result i
LPHA/gem5.opt
scons --verbose build/ALPHA/gem5.opt FULL_SYSTEM=True
PROTOCOL=MOESI_CMP_directory
All of them failed to produce a binary. Any ideas why?
From: Kirtika Ruchandani
To: Iordan Alexandru ; gem5 users mailing list
Sent: Tuesday, April 3, 2012 11:
looking through SConstruct and SConscripts to find something wrong.
Alexandru
From: Ali Saidi
To: Iordan Alexandru ; gem5 users mailing list
Sent: Tuesday, April 3, 2012 3:59 PM
Subject: Re: [gem5-users] Building error
Did any of them produce more output
conftest_11.c <-
|
|#include
|
|
gcc -o build/.scons_config/conftest_11.o -c -pipe -fno-strict-aliasing -Wall
-Wno-sign-compare -Wundef -Iext -I/usr/include/python2.7
build/.scons_config/conftest_11.c
scons: Configure: yes
Alexandru
From: Ali Saidi
To
and was causing
a force exit no matter what. In the end it was the merger that screwed up this.
I am sorry if you wasted to much time on this.
Best regards,
Alexandru Iordan
From: Iordan Alexandru
To: "sa...@umich.edu" ; gem5 users mailing li
Hello
I also faced this problem. In my case it was caused by the fact that the
parameters at the system level (number_of_cores, number_of_L2s, number_of_NoCs
etc. in power.xml file) that had a value of 1 were not described afterwards in
detailed. If you post your power.xml file I can take a lo
Is it possible for you to give some more details on how to implemented what you
said there? How should I update gem5/system/alpha/console/console.c so that I
can use more than 2 GB of main memory in my simulations?
Thanks in advance!
Best regards,
Alexandru Iordan___
2, 2012 8:48 PM
Subject: Re: [gem5-users] How to configure more than 1GB physical memory on
ALPHA_FS
You should just be able to compile it and use the compiled version instead of
the one you downloaded from the website.
Ali
On 02.10.2012 13:44, Iordan Alexandru wrote:
Is it possible for you
Never mind. I figured it out. I moved the newly compiled console binary to the
binary folder of the full_system_image_files. Now it works!
From: Iordan Alexandru
To: gem5 users mailing list
Sent: Wednesday, October 3, 2012 10:41 AM
Subject: Re: [gem5-users
Hello
I am new to fast forwarding and I have been struggling with a problem for some
days. I am trying to reduce the simulation time for my multiprocessor FS
simulations and in order to do that I want to fast forward to a specific
instruction count and execute in detailed mode from that point.
Hope that helps,
Joel
On Wed, Jun 22, 2011 at 9:01 AM, Iordan Alexandru wrote:
Hello
>
>I am new to fast forwarding and I have been struggling with a problem for some
>days. I am trying to reduce the simulation time for my multiprocessor FS
>simulations and in order to do that
Hello
All operations listed on http://www.gem5.org/M5ops can be called like functions
(m5_checkpoint, m5_reset_stats, m5_dump_stats, m5_dumpreset_stats etc.) in your
source code where you need them. However, in order to make them work you need
to
do two things:
- you need to include m5op.h in
29 matches
Mail list logo
