Hello

I know this was discussed before but I did not find anybody who actually make 
it work. Just like others before me I am facing difficulties in implementing 
the back and forth switch.

What I did so far:

- I added the following to the configs/common/Simulation.py (the red code is 
what I added)
...............................................................................................................................................................
            ## Adjust max tick based on our starting tick
            maxtick = maxtick - int(cpts[cpt_num - 1])
            checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1])

    simple_cpu_class = AtomicSimpleCPU
    detailed_cpu_class = DerivO3CPU
    detailed_switch_cpus = [detailed_cpu_class(defer_registration=True, 
cpu_id=(np+i)) for i in xrange(np)]
    simple_switch_cpus = [simple_cpu_class(defer_registration=True, 
cpu_id=(2*np+i)) for i in xrange(np)]
    for i in xrange(np):
        detailed_switch_cpus[i].system =  testsys
        simple_switch_cpus[i].system =  testsys

        if not buildEnv['FULL_SYSTEM']:
                detailed_switch_cpus[i].workload = testsys.cpu[i].workload
                simple_switch_cpus[i].workload = testsys.cpu[i].workload 
    
        detailed_switch_cpus[i].clock = testsys.cpu[0].clock
        simple_switch_cpus[i].clock = testsys.cpu[0].clock
        
    testsys.switch_detailed = detailed_switch_cpus
    testsys.switch_simple = simple_switch_cpus
 
    switch_cpu_list = [(testsys.cpu[i], detailed_switch_cpus[i] ) for i in 
xrange(np)]
    switch_cpu_list1 = [(detailed_switch_cpus[i], simple_switch_cpus[i] ) for i 
in xrange(np)]
    switch_cpu_list2 = [(simple_switch_cpus[i], detailed_switch_cpus[i] ) for i 
in xrange(np)]
    
    m5.instantiate(checkpoint_dir)
...............................................................................................................................................................

else: # no checkpoints being taken via this script
        if options.fast_forward:
            m5.stats.reset()
        print "**** REAL SIMULATION ****"
        exit_event = m5.simulate(maxtick)
        exit_cause = exit_event.getCause()
        if exit_cause == "switchcpu":
                print "Switchcpus  Atomic -> Detailed"

                m5.stats.dump()
                m5.stats.reset()
                m5.changeToTiming(testsys)
                m5.drain(testsys)
                m5.switchCpus(switch_cpu_list)
                m5.resume(testsys)

                exit_event = m5.simulate(maxtick-m5.curTick())
                exit_cause = exit_event.getCause()
        while exit_cause == "switchcpu":
                print "Switchcpus Detailed -> Atomic"

                m5.stats.dump()
                m5.stats.reset()
                m5.changeToAtomic(testsys)
                m5.drain(testsys)            
                m5.switchCpus(switch_cpu_list1)
                m5.resume(testsys)
                
                exit_event = m5.simulate(maxtick-m5.curTick())
                exit_cause = exit_event.getCause()

                if exit_cause == "switchcpu":
                        print "Switchcpus  Atomic -> Detailed"

                        m5.stats.dump()#"Atomic")
                        m5.stats.reset()
                        m5.changeToTiming(testsys)
                        m5.drain(testsys)            
                        m5.switchCpus(switch_cpu_list2)
                        m5.resume(testsys)
                        
                        exit_event = m5.simulate(maxtick-m5.curTick())
                        exit_cause = exit_event.getCause()

while exit_event.getCause() == "checkpoint":
            m5.checkpoint(joinpath(cptdir, "cpt.%d"))
...............................................................................................................................................................



- I modified the BaseCPU::takeOverFrom function in src/cpu/base.cc so that port 
assignment is performed even if the newCPU was previously connected in the 
system:

...............................................................................................................................................................
 if (1){        
        Port *peer = oldCPU->getPort("icache_port")->getPeer();
        ic->setPeer(peer);
        peer->setPeer(ic);
    }

    if (1) {        
        Port *peer = oldCPU->getPort("dcache_port")->getPeer();
        dc->setPeer(peer);
        peer->setPeer(dc);
    }
...............................................................................................................................................................

I start the simulation with AtomicSimpleCPU model:

./build/ALPHA_FS/gem5.opt --outdir=test configs/example/fs.py -n 2 --caches 
--l2cache

I trigger the switches from terminal and the first 2 switches (first pass in 
the while loop in Simulation.py) works fine, but after that the simulation 
appears to hang. I ran it through GDB and it appears that the simulation is 
still running but is running extremely slow. I can't figure it out what is 
going wrong. Am I approaching this the wrong way? Am I doing something wrong 
when I am setting up the switching environment? Any suggestions?

Thanks in advance!

Alexandru



- I modified the 
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