[gem5-users] Mounting second image FS

Hi all, I have the standard setup with the x86 disk image containing parsec. I'm trying to add benchmarks and because that image has no more space, I created new images with the extra benchmarks. Those images don't have the OS, therefore the primary x86 image needs to boot and I need to mount t

[gem5-users] Gem5 freezing with x86 timing cpu

Hi all, I have this weird problem where gem5 starts executing a benchmark (some parsec and some others) or starts booting in FS mode but then just freezes. I was wondering how you would recommend getting to the bottom of this. Can I figure out what it's doing? I know I can attach a debugger but

[gem5-users] Valid thread ID assertion

Hi all, Running the latest stable gem5, ghb and tagged prefetchers cause assertions to fail when uses as last level (L2) prefetchers with the classic memory model in FS Alpha: gem5.opt: build/ALPHA_MESI_Two_Level/mem/request.hh:575: int Request::threadId() const: Assertion `privateFlags.isSet(VA

[gem5-users] MSHR assertion fail

Hi all and happy new year! I'm using the latest version of gem5 dev and stable for last-level cache prefetchers using the classic memory model and ALPHA. GHB and my own prefetcher in some edits produce the following: gem5.opt: build/ALPHA_MESI_Two_Level/mem/cache/mshr.hh:278: MSHR::Target* MSHR:

[gem5-users] Stride prefetcher across pages

Hi all, I noticed that the latest gem5-dev after the reorganization of prefetcher structures, removed the option to perform strided prefetching across pages. Now the prefetcher remains in the same page. Is this assumption necessary for other components? Forcing the option back produces a seg faul

[gem5-users] MSHR assertion fail

Hi all,   First off thanks for your help with my previous question. However, the sad thing about fixing a bug is that another problem is revealed :-) Currently my prefetcher works fine when it can only issue within the same page. When it is free to prefetch from different pages (while checking th

Re: [gem5-users] MSHR assertion fail

Hi George, Are you using Ruby (based on your binary it seems so)? If so, could you try the vanilla non-Ruby gem5 memory system? Andreas From: George Michelogiannakis via gem5-users Reply-To: George Michelogiannakis , gem5 users mailing list Date: Tuesday, 27 January 2015 19:44 To: Gem5 Users Ma

[gem5-users] M5 Fs utility workbegin

Hello Gem5 community, I'm trying to use the M5 utility meant for full system mode to signal work begin and end. I see in the documentation that the utility supports these parameters: - workbegin: Cause an exit evet of type, “workbegin”, that could be used to mark the begining of an ROI.

[gem5-users] Re: M5 Fs utility workbegin

Indeed there is a way to signal workbegin and workend from the program itself with m5 ops. But I'm trying to avoid recompiling a whole bunch of code to make it happen, though I can do that too. If there is a way to simulate workbegin and workend from the command line great, otherwise no worries

[gem5-users] Re: M5 Fs utility workbegin

Hello Jason and everyone, I'll add the fix to my todo list :) But before then, I'm confused by something. Thanks for the link to hooks and indeed I "m5_work_begin(0,0);. I recompiled the benchmarks I had with work begin and end. It's just adding "m5_work_begin(0,0)" and "m5_work_end(0,0)" at the

[gem5-users] Libthreads for Gem5

Good morning everyone, Does anyone know if "m5threads" is available for RISC-V? I'm trying to compile an OpenMP code for RISC-V, hopefully avoiding FS. Thank you ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5

[gem5-users] Prefetchers in LLC assertion fail

Hello everyone, I tried using the pre fetchers already in Gem5 (mostly stride and tagged) next to the L2 in the simple cache model (no Ruby) with just L1s and a single L2. From past emails I figured this should be supported, but I'm getting assertion failures in regards to the number of context

[gem5-users] Memory size with DRAMSim2

Hi all, when I run gem5 with dramsim2, what is the easiest way to increase the memory size? Should I increase the number of channels in DRAMSim2's config, or use a parameter in gem5 that'll trickle down to DRAMSim2 to increase the number of ranks? Thank you,  George M

[gem5-users] PARSEC in Syscall

Hi everyone!    I've been trying to run as many PARSEC benchmarks as I can in sys call emulation mode with proper compilation and with m5threads and --static. There are some peculiarities in specific benchmarks that I was hoping some people in here have faced already :-) I couldn't really find a

Re: [gem5-users] running splash2 on se mode

>From my experience this happens if you don't link right with gem5's pthread >library. Check your makefile and remove -lpthreads and replace with wherever >your libpthreads.a is when you are linking. On Saturday, October 25, 2014 3:33 AM, fatemeh rafieenezhad via gem5-users wrote: Hi,