[gem5-users] Clarification minor CPU “in-order”

Hello everybody, According to [1] the gem5 minor CPU is an in-order processor model and features a scoreboarding algorithm. However, according to [2] scoreboarding is a dynamic scheduling algorithm with out-of-order execution like the Tomasulo algorithm. Therefore, I have the following two questio

[gem5-users] RV32 support

Hello everybody, I know that this question has been already asked but I want to ask again what the current support for RISC-V in 32bit mode is – particularly for the FS mode. [1] suggests that no support is implemented currently while [2] already presented an implementation in 2018. The bit width