Hello everybody, I know that this question has been already asked but I want to ask again what the current support for RISC-V in 32bit mode is – particularly for the FS mode. [1] suggests that no support is implemented currently while [2] already presented an implementation in 2018. The bit width in the generated decoder-ns.cc.inc files seem to be fixed for 64bit. The arch of my 32bit binary seems to be correctly identified as Riscv32 in the fs_workload class but the execution does not seem to exhibit a 32bit ISA semantic. If RV32 in FS mode is supported, how do I use it correctly?
Many thanks in advance and best regards, Felix Böseler [1] https://gem5.atlassian.net/browse/GEM5-923 [2] Scheffel, Robert (2018): Simulation of RISC-V based Systems in gem5. Diplomarbeit. Technische Universität Dresden, Dresden.
_______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
