Hello.
I was trying to find how the virtual (logical) addresses are calculated and
passed on to cpu.
In the load/store queee, after a request object is created, then the
corresponding instruction is assigned a effective address from this request
object, something like inst->effaddr=req->getVirt(
On 2/5/2024 10:41 AM, Nazmus Sakib via gem5-users wrote:
Hello.
I was trying to find how the virtual (logical) addresses are calculated and
passed on to cpu.
In the load/store queee, after a request object is created, then the corresponding instruction is assigned a effective
address from this
I am trying to see how small I can set the cacheline size (gem5 ARM, test
binary is aarch64)
When I set it to 4 bytes, I get a page fault for address 0x400c00. By going
through bunch of debugging (using print of my own and debug flags), I think the
problem is, when trying to generate address 0x4
On 2/5/2024 1:39 PM, Nazmus Sakib wrote:
I am trying to see how small I can set the cacheline size (gem5 ARM, test
binary is aarch64)
When I set it to 4 bytes, I get a page fault for address 0x400c00. By going through bunch of debugging (using print of
my own and debug flags), I think the probl
